32 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Interrupts
5.3 Interrupts and Exceptions -
Operation
5.3.1 Interrupt/Exception Handling
The following sequence of events occurs when an interrupt
or exception event is triggered:
1. Assuming that all the interrupt signals are initially low
(idle or inactive state) and the processor is executing the
main code, a rising edge on any one of the interrupt lines
is registered by the NVIC. The interrupt line is now in a
pending state waiting to be serviced by the CPU.
2. On detecting the interrupt request signal from the NVIC,
the CPU stores its current context by pushing the con-
tents of the CPU registers onto the stack.
3. The CPU also receives the exception number of the trig-
gered interrupt from the NVIC. All interrupts and excep-
tions have a unique exception number, as given in
Table 5-1. By using this exception number, the CPU
fetches the address of the specific exception handler
from the vector table.
4. The CPU then branches to this address and executes
the exception handler that follows.
5. Upon completion of the exception handler, the CPU reg-
isters are restored to their original state using stack pop
operations; the CPU resumes the main code execution.
Figure 5-2. Interrupt Handling When Triggered
When the NVIC receives an interrupt request while another
interrupt is being serviced or receives multiple interrupt
requests at the same time, it evaluates the priority of all
these interrupts, sending the exception number of the high-
est priority interrupt to the CPU. Thus, a higher priority inter-
rupt can block the execution of a lower priority ISR at any
time.
Exceptions are handled in the same way that interrupts are
handled. Each exception event has a unique exception num-
ber, which is used by the CPU to execute the appropriate
exception handler.
5.3.2 Level and Pulse Interrupts
NVIC supports both level and pulse signals on the interrupt
lines (IRQ0 to IRQ8). The classification of an interrupt as
level or pulse is based on the interrupt source.
Figure 5-3. Level Interrupts
Figure 5-4. Pulse Interrupts
Figure 5-3 and Figure 5-4 show the working of level and
pulse interrupts, respectively. Assuming the interrupt signal
is initially inactive (logic low), the following sequence of
events explains the handling of level and pulse interrupts:
1. On a rising edge event of the interrupt signal, the NVIC
registers the interrupt request. The interrupt is now in the
pending state, which means the interrupt requests have
not yet been serviced by the CPU.
2. The NVIC then sends the exception number along with
the interrupt request signal to the CPU. When the CPU
starts executing the ISR, the pending state of the inter-
rupt is cleared.
3. When the ISR is being executed by the CPU, one or
more rising edges of the interrupt signal are logged as a
single pending request. The pending interrupt is serviced
again after the current ISR execution is complete (see
Figure 5-4 for pulse interrupts).
4. If the interrupt signal is still high after completing the ISR,
it will be pending and the ISR is executed again.
Figure 5-3 illustrates this for level triggered interrupts,
where the ISR is executed as long as the interrupt signal
is high.
Rising Edge on Interrupt Line is
registered by the NVIC
CPU detects the request signal
from NVIC and stores its
current context by pushing
contents onto the stack
CPU receives exception
number of triggered interrupt
and fetches the address of the
specific exception handle from
vector table.
CPU branches to the received
address and executes
exception handler
CPU registers are restored
using stack upon completion of
exception handler.
IRQn
CPU
Execution
State
main
ISR ISR
main
ISR
main
IRQn is still high
IRQn
CPU
Execution
State
main
ISR
main
ISR
main
ISR
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