PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 123
Timer, Counter, and PWM
16.4 TCPWM Registers
Table 16-9. List of TCPWM Registers
Register Comment Features
TCPWM_CTRL TCPWM control register Enables the counter block
TCPWM_CMD TCPWM command register Generates software events
TCPWM_INTR_CAUSE TCPWM counter interrupt cause register Determines the source of the combined interrupt signal
TCPWM_CNT_CTRL Counter control register
Configures counter mode, encoding modes, one shot mode,
switching, kill feature, dead time, clock pre-scaling, and counting
direction
TCPWM_CNT_STATUS Counter status register
Reads the direction of counting, dead time duration, and clock
pre-scaling; checks if the counter is running
TCPWM_CNT_COUNTER Count register Contains the 16-bit counter value
TCPWM_CNT_CC Counter compare/capture register
Captures the counter value or compares the value with counter
value
TCPWM_CNT_CC_BUFF Counter buffered compare/capture register Buffer register for counter CC register; switches period value
TCPWM_CNT_PERIOD Counter period register Contains upper value of the counter
TCPWM_CNT_PERIOD_BUFF Counter buffered period register Buffer register for counter period register; switches compare value
TCPWM_CNT_TR_CTRL0 Counter trigger control register 0 Selects trigger for specific counter events
TCPWM_CNT_TR_CTRL1 Counter trigger control register 1 Determine edge detection for specific counter input signals
TCPWM_CNT_TR_CTRL2 Counter trigger control register 2 Controls counter output lines upon CC, OV, and UN conditions
TCPWM_CNT_INTR Interrupt request register Sets the register bit when TC or CC condition is detected
TCPWM_CNT_INTR_SET Interrupt set request register Sets the corresponding bits in interrupt request register
TCPWM_CNT_INTR_MASK Interrupt mask register Mask for interrupt request register
TCPWM_CNT_INTR_MASKED Interrupt masked request register Bitwise AND of interrupt request and mask registers
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