PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 31
5. Interrupts
The ARM Cortex-M0 (CM0) CPU in PSoC
®
4 supports interrupts and exceptions. Interrupts refer to those events generated
by peripherals external to the CPU such as timers, serial communication block, and port pin signals. Exceptions refer to those
events that are generated by the CPU such as memory access faults and internal system timer events. Both interrupts and
exceptions result in the current program flow being stopped and the exception handler or interrupt service routine (ISR) being
executed by the CPU. The device provides a unified exception vector table for both interrupt handlers/ISR and exception han-
dlers.
5.1 Features
PSoC 4 supports the following interrupt features:
■ Supports 9 interrupts
■ Nested vectored interrupt controller (NVIC) integrated with CPU core, yielding low interrupt latency
■ Vector table may be placed in either flash or SRAM
■ Configurable priority levels from 0 to 3 for each interrupt
■ Level-triggered and pulse-triggered interrupt signals
5.2 How It Works
Figure 5-1. PSoC 4 Interrupts Block Diagram
Figure 5-1 shows the interaction between interrupt signals and the Cortex-M0 CPU. PSoC 4 has nine interrupts; these inter-
rupt signals are processed by the NVIC. The NVIC takes care of enabling/disabling individual interrupts, priority resolution,
and communication with the CPU core. The exceptions are not shown in Figure 5-1 because they are part of CM0 core gen-
erated events, unlike interrupts, which are generated by peripherals external to the CPU.
Nested
Vectored
Interrupt
Controller
(NVIC)
Cortex-M0
Processor Core
IRQ0
Cortex-M0 Processor
IRQ1
IRQ8
Interrupt signals
from PSoC 4
on-chip peripherals
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