74 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Watchdog Timer
The IGNORE_BITS in the WDT_MATCH register can be used to reduce the entire WDT counter period. The ignore bits can
specify the number of MSBs that need to be discarded. For example, if the IGNORE_BITS value is 3, then the WDT counter
becomes a 13-bit counter. For details, see the WDT_COUNTER, WDT_MATCH, and SRSS_INTR registers in the
PSoC 4000
Family: PSoC 4 Registers TRM.
When the WDT is used to protect against system crashes, clearing the WDT interrupt bit to reset the watchdog must be done
from a portion of the code that is not directly associated with the WDT interrupt. Otherwise, even if the main function of the
firmware crashes or is in an endless loop, the WDT interrupt vector can still be intact and feed the WDT periodically.
The safest way to use the WDT against system crashes is to:
■ Configure the watchdog reset period such that firmware is able to reset the watchdog at least once during the period, even
along the longest firmware delay path.
■ Reset the watchdog by clearing the interrupt bit regularly in the main body of the firmware code by writing a '1' to the
WDT_MATCH bit in SRSS_INTR register.
■ It is not recommended to reset watchdog in the WDT interrupt service routine (ISR), if WDT is being used as a reset
source to protect the system against crashes. Hence, it is not recommended to use WDT reset feature and ISR together.
Follow these steps to use WDT as a periodic interrupt generator:
1. Write the desired IGNORE_BITS in the WDT_MATCH register to set the counter resolution.
2. Write the desired match value to the WDT_MATCH register.
3. Clear the WDT_MATCH bit in SRSS_INTR to clear any pending WDT interrupt.
4. Enable the WDT interrupt by setting the WDT_MATCH bit in SRSS_INTR_MASK
5. Enable global WDT interrupt in the CM0_ISER register (See the Interrupts chapter on page 31 for details).
6. In the ISR, clear the WDT interrupt and add the desired match value to the existing match value. By doing so, another
periodic interrupt will be generated when the counter reaches the new match value.
For more details on interrupts, see the Interrupts chapter on page 31.
12.3.1 Enabling and Disabling WDT
The watchdog counter is a free-running counter that cannot be disabled. However, it is possible to disable the watchdog reset
by writing a key '0xACED8865' to the WDT_DISABLE_KEY register. Writing any other value to this register will enable the
watchdog reset. If the watchdog system reset is disabled, the firmware does not have to periodically reset the watchdog to
avoid a system reset. The watchdog counter can still be used as an interrupt source or wakeup source. The only way to stop
the counter is to disable the ILO by clearing the ENABLE bit in the CLK_ILO_CONFIG register. The watchdog reset must be
disabled before disabling the ILO. Otherwise, any register write to disable the ILO will be ignored. Enabling the watchdog
reset will automatically enable the ILO.
Note Disabling the WDT reset is not recommended if:
■ Protection is required against firmware crashes
■ The power supply can produce sudden brownout events that may compromise the CPU functionality
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