Cypress PSoC 4000 Series - Pulse Width Modulation Pseudo-Random Mode

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 121
Timer, Counter, and PWM
16.3.6 Pulse Width Modulation Pseudo-Random Mode
This mode uses the linear feedback shift register (LFSR). LFSR is a shift register whose input bit is a linear function of its pre-
vious state.
16.3.6.1 Block Diagram
Figure 16-16. PWM-PR Mode Block Diagram
16.3.6.2 How It Works
The counter register is used to implement LFSR with the polynomial: x
16
+x
14
+x
13
+x
11
+1, as shown in Figure 16-17. It gener-
ates all the numbers in the range [1, 0xFFFF] in a pseudo-random sequence. Note that the counter register should be initial-
ized with a non-zero value.
Figure 16-17. Pseudo-Random Sequence Generation using Counter Register
PERIOD
LFSR / COUNTER
COMPARE
BUFFER COMPARE
==
reload
start
stop
switch
CC
TC
counter_clock
BUFFER PERIOD
<
line_out
0
10 0 00 0000111 1111