Cypress PSoC 4000 Series - 1.2 Features; 1.3 CPU System

14 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Introduction
Figure 1-1. PSoC 4000 Family Block Diagram
1.2 Features
The PSoC 4000 family has these major components:
■ 32-bit Cortex-M0 CPU with single-cycle multiply, deliver-
ing up to 14 DMIPS at 16 MHz
■ Up to 16 KB flash and 2 KB SRAM
■ A center-aligned pulse-width modulator (PWM) with
complementary, dead-band programmable outputs
■ I2C communication block with slave, master, and multi-
master operating modes
■ CapSense
■ Low-power operating modes: Sleep and Deep-Sleep
■ Programming and debugging system through serial wire
debug (SWD)
■ Two current sourcing/sinking DACs (IDACs)
■ Comparator with 1.2 V reference
■ Fully supported by PSoC Creator™ IDE tool
1.3 CPU System
1.3.1 Processor
The heart of the PSoC 4 is a 32-bit Cortex-M0 CPU core
running up to 16 MHz for PSoC 4000. It is optimized for low-
power operation with extensive clock gating. It uses 16-bit
instructions and executes a subset of the Thumb-2 instruc-
tion set. This instruction set enables fully compatible binary
upward migration of the code to higher performance proces-
sors such as Cortex M3 and M4.
The CPU has a hardware multiplier that provides a 32-bit
result in one cycle.
1.3.2 Interrupt Controller
The CPU subsystem includes a nested vectored interrupt
controller (NVIC) with nine interrupt inputs and a wakeup
interrupt controller (WIC), which can wake the processor
from Deep-Sleep mode.
Deep Sleep
Active/ Sleep
CPU Subsystem
SRAM
2 KB
SRAM Controller
ROM
4 KB
ROM Controller
Flash
16 KB
Read Accelerator
SPCIFSWD/TC
NVIC, IRQMX
Cortex
M0
16 MHz
MUL
System Interconnect (
Single/Multi Layer AHB
)
I/O Subsystem
20 x GPIOs
IOSS GPIO (4x ports)
Peripherals
Peripheral Interconnect (MMIO)
PCLK
PSoC 4000
32-bit
AHB-Lite
System Resources
Lite
Power
Clock
WDT
ILO
Reset
Clock Control
IMO
Sleep Control
PWRSYS
REFPOR
WIC
Reset Control
XRES
1x SCB-I2C
CapSense
High Speed I/O Matrix
Power Modes
1x TCPWM