26 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Cortex-M0 CPU
4.2 Block Diagram
Figure 4-1. PSoC 4 CPU Subsystem Block Diagram
4.3 How It Works
The Cortex-M0 is a 32-bit processor with a 32-bit data path, 32-bit registers, and a 32-bit memory interface. It supports most
16-bit instructions in the Thumb instruction set and some 32-bit instructions in the Thumb-2 instruction set.
The processor supports two operating modes (see “Operating Modes” on page 28). It has a single-cycle 32-bit multiplication
instruction.
4.4 Address Map
The ARM Cortex-M0 has a fixed address map allowing access to memory and peripherals using simple memory access
instructions. The 32-bit (4 GB) address space is divided into the regions shown in Table 4-1. Note that code can be executed
from the code and SRAM regions.
Table 4-1. Cortex-M0 Address Map
Address Range Name Use
0x00000000 - 0x1FFFFFFF Code
Program code region. You can also place data here. Includes the exception vector table,
which starts at address 0.
0x20000000 - 0x3FFFFFFF SRAM Data region. You can also execute code from this region.
0x40000000 - 0x5FFFFFFF Peripheral All peripheral registers. You cannot execute code from this region.
0x60000000 - 0xDFFFFFFF Not used.
0xE0000000 - 0xE00FFFFF PPB Peripheral registers within the CPU core.
0xE0100000 - 0xFFFFFFFF Device PSoC 4 implementation-specific.
ARM Cortex-M0 CPU
System Interconnect
Flash
Accelerator
SRAM
Controller
SROM
Controller
DAP
CPU Subsystem
Flash SRAM SROM
AHB Bridge
Test
Controller
Fixed Interrupts
DSI Interrupts
Flash
Programming
Interface
CPU & Memory
Subsystem
Interrupt
MUX
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