Cypress PSoC 4000 Series - Block Diagram

62 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Power Supply and Monitoring
9.1 Block Diagram
Figure 9-1. Power System Block Diagram
The Active digital regulator allows the external V
DD
supply to
be regulated to the nominal 1.8 V required for the digital
core. The output pin of this regulator has a specific capacitor
requirement, as shown in Figure 9-1. This Active digital reg-
ulator is designed to supply the internal circuits only; there-
fore, it
should not be loaded externally.
The primary regulated supply, labeled V
CCD
, can be config-
ured for internal regulation or can be directly supplied by the
pin. In internal regulation mode, V
DD
can vary between
1.8 V and 5.5 V and the on-chip regulators generate the
other low-voltage supplies.
In direct supply configuration, V
CCD
and V
DD
must be
shorted together and connected to a supply of 1.71 V to
1.89 V. The Active digital regulator is still powered up and
enabled by default. It must be disabled by the firmware to
reduce power consumption; see 9.3.1.1 Active Digital Regu-
lator.
The V
DDIO
pin, available in certain package types, provides
a separate voltage domain for the I2C pins. The chip can
thus communicate with an I2C system, running at a different
voltage (where V
DDIO
 V
DD
). For example, V
DD
can be
3.3 V and V
DDIO
can be 1.8 V. See the device datasheet for
details.
One additional regulator is used to provide power in the
Deep-Sleep mode.
Digital
Regulator
V
DD
0.1 uF
1 uF
V
DD
V
CCD
Active
Domain
Examples: CPU,
IMO, Flash
Quiet
Regulator
Deep-Sleep
Regulator
Bandgap
Voltage
Reference
Deep-Sleep
Domain
Examples: ILO,
I2C
V
SS
Note: Do not connect
external load to V
CCD
1 uF
V
DDIO
0.1 uF
1 uF