78 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Reset System
13.1.4 Software Initiated Reset
Software initiated reset (SRES) is a mechanism that allows a software-driven reset. The Cortex-M0 application interrupt and
reset control register (CM0_AIRCR) forces a device reset when a ‘1’ is written into the SYSRESETREQ bit. CM0_AIRCR
requires a value of A05F written to the top two bytes for writes. Therefore, write A05F0004 for the reset.
The RESET_SOFT status bit of the RES_CAUSE register is set when a software reset occurs. This bit remains set until
cleared or until a POR, XRES, or BOD reset; for example, in the case of a device power cycle. All other resets leave this bit
untouched.
13.1.5 External Reset
External reset (XRES) is a user-supplied reset that causes immediate system reset when asserted. The XRES pin is active
low – a high voltage on the pin has no effect and a low voltage causes a reset. The pin is pulled high inside the device. XRES
is available as a dedicated pin in most of the devices. For detailed pinout, refer to the pinout section of the device datasheet.
The XRES pin holds the device in reset while held active. When the pin is released, the device goes through a normal boot
sequence. The logical thresholds for XRES and other electrical characteristics, are listed in the Electrical Specifications sec-
tion of the device datasheet.
XRES events do not set a reset cause status bit, but can be partially inferred by the absence of any other reset source. If no
other reset event is detected, then the reset is caused by POR, BOD, or XRES.
13.1.6 Protection Fault Reset
Protection fault reset (PROT_FAULT) detects unauthorized protection violations and causes a device reset if they occur. One
example of a protection fault is if a debug breakpoint is reached while executing privileged code. For details about privilege
code, see “Privileged” on page 67.
The RESET_PROT_FAULT bit of the RES_CAUSE register is set when a protection fault occurs. This bit remains set until
cleared or until a POR, XRES, or BOD reset; for example, in the case of a device power cycle. All other resets leave this bit
untouched.
13.2 Identifying Reset Sources
When the device comes out of reset, it is often useful to know the cause of the most recent or even older resets. This is
achieved in the device primarily through the RES_CAUSE register. This register has specific status bits allocated for some of
the reset sources. The RES_CAUSE register supports detection of watchdog reset, software reset, and protection fault reset.
It does not record the occurrences of POR, BOD, or XRES. The bits are set on the occurrence of the corresponding reset and
remain set after the reset, until cleared or a loss of retention, such as a POR reset, external reset, or brownout detect.
If the RES_CAUSE register cannot detect the cause of the reset, then it can be one of the non-recorded and non-retention
resets: BOD, POR, or XRES. These resets cannot be distinguished using on-chip resources.
13.3 Register List
Table 13-1. Reset System Register List
Register Name Description
WDT_DISABLE_KEY Disables the WDT when 0XACED8865 is written, for any other value WDT works normally
CM0_AIRCR
Cortex-M0 Application Interrupt and Reset Control Register - This register allows initiation of software resets,
among other Cortex-M0 functions.
RES_CAUSE Reset Cause Register - This register captures the cause of recent resets.
To Next Page
Loading...
