72 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Power Modes
11.5 Low-Power Mode Entry and Exit
A Wait For Interrupt (WFI) instruction from the Cortex-M0 (CM0) triggers the transitions into Sleep and Deep-Sleep mode. The
Cortex-M0 can delay the transition into a low-power mode until the lowest priority ISR is exited (if the SLEEPONEXIT bit in the
CM0 System Control Register is set).
The transition to Sleep and Deep-Sleep modes are controlled by the flags SLEEPDEEP in the CM0 System Control Register
(CM0_SCR).
■ Sleep is entered when the WFI instruction is executed, SLEEPDEEP = 0.
■ Deep-Sleep is entered when the WFI instruction is executed, SLEEPDEEP = 1.
The LPM READY bit in the PWR_CONTROL register shows the status of Deep-Sleep regulator. If the firmware tries to enter
Deep-Sleep mode before the regulators are ready, then PSoC 4 goes to Sleep mode first, and when the regulators are ready,
the device enters Deep-Sleep mode. This operation is automatically done in hardware.
In Sleep and Deep-Sleep modes, a selection of peripherals are available (see Table 11-3), and firmware can either enable or
disable their associated interrupts. Enabled interrupts can cause wakeup from low-power mode to Active mode. Additionally,
any RESET returns the system to Active mode. See the Interrupts chapter on page 31 and the Reset System chapter on
page 77 for details.
11.6 Register List
Table 11-4. Power Mode Register List
Register Name Description
CM0_SCR System Control - Sets or returns system control data.
PWR_CONTROL Power Mode Control - Controls the device power mode options and allows observation of current state.
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