PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 25
4. Cortex-M0 CPU
The PSoC
®
4 ARM Cortex-M0 core is a 32-bit CPU optimized for low-power operation. It has an efficient three-stage pipeline,
a fixed 4-GB memory map, and supports the ARMv6-M Thumb instruction set. The Cortex-M0 also features a single-cycle 32-
bit multiply instruction and low-latency interrupt handling. Other subsystems tightly linked to the CPU core include a nested
vectored interrupt controller (NVIC), a SYSTICK timer, and debug.
This section gives an overview of the Cortex-M0 processor. For more details, see the ARM Cortex-M0 user guide or technical
reference manual, both available at www.arm.com.
4.1 Features
The PSoC 4 Cortex-M0 has the following features:
■ Easy to use, program, and debug, ensuring easier migration from 8- and 16-bit processors
■ Operates at up to 0.9 DMIPS/MHz; this helps to increase execution speed or reduce power
■ Supports the Thumb instruction set for improved code density, ensuring efficient use of memory
■ NVIC unit to support interrupts and exceptions for rapid and deterministic interrupt response
■ Extensive debug support including:
❐ SWD port
❐ Breakpoints
❐ Watchpoints
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