36 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Interrupts
5.7 Enabling and Disabling
Interrupts
The NVIC provides registers to individually enable and dis-
able the nine interrupts in software. If an interrupt is not
enabled, the NVIC will not process the interrupt requests on
that interrupt line. The Interrupt Set-Enable Register
(CM0_ISER) and the Interrupt Clear-Enable Register
(CM0_ICER) are used to enable and disable the interrupts
respectively. These are 32-bit wide registers and each bit
corresponds to the same numbered interrupt. These regis-
ters can also be read in software to get the enable status of
the interrupts. Table 5-4 shows the register access proper-
ties for these two registers. Note that writing zero to these
registers has no effect.
The CM0_ISER and CM0_ICER registers are applicable
only for interrupts IRQ0 to IRQ8. These registers cannot be
used to enable or disable the exception numbers 1 to 11.
The 15 exceptions have their own support for enabling and
disabling, as explained in “Exception Sources” on page 33.
The PRIMASK register in Cortex-M0 (CM0) CPU can be
used as a global exception enable register to mask all the
configurable priority exceptions irrespective of whether they
are enabled. Configurable priority exceptions include all the
exceptions except Reset, NMI, and HardFault listed in
Table 5-1. They can be configured to a priority level between
0 and 3, 0 being the highest priority and 3 being the lowest
priority. When the PM bit (bit 0) in the PRIMASK register is
set, none of the configurable priority exceptions can be ser-
viced by the CPU, though they can be in the pending state
waiting to be serviced by the CPU after the PM bit is cleared.
5.8 Exception States
Each exception can be in one of the following states.
The Interrupt Control State Register (CM0_ICSR) contains
status bits describing the various exceptions states.
■ The VECTACTIVE bits ([8:0]) in the CM0_ICSR store the
exception number for the current executing exception.
This value is zero if the CPU does not execute any
exception handler (CPU is in thread mode). Note that the
value in VECTACTIVE bit fields is the same as the value
in bits [8:0] of the Interrupt Program Status Register
(IPSR), which is also used to store the active exception
number.
■ The VECTPENDING bits ([20:12]) in the CM0_ICSR
store the exception number of the highest priority pend-
ing exception. This value is zero if there are no pending
exceptions.
■ The ISRPENDING bit (bit 22) in the CM0_ICSR indi-
cates if a NVIC generated interrupt (IRQ0 to IRQ8) is in
a pending state.
5.8.1 Pending Exceptions
When a peripheral generates an interrupt request signal to
the NVIC or an exception event occurs, the corresponding
exception enters the pending state. When the CPU starts
executing the corresponding exception handler routine, the
exception is changed from the pending state to the active
state.
The NVIC allows software pending of the nine interrupt lines
by providing separate register bits for setting and clearing
the pending states of the interrupts. The Interrupt Set-Pend-
ing register (CM0_ISPR) and the Interrupt Clear-Pending
register (CM0_ICPR) are used to set and clear the pending
status of the interrupt lines. These are 32-bit wide registers
and each bit corresponds to the same numbered interrupt.
Table 5-3. Interrupt Priority Register Bit Definitions
Bits Name Description
7:6 PRI_N0 Priority of interrupt number N.
15:14 PRI_N1 Priority of interrupt number N+1.
23:22 PRI_N2 Priority of interrupt number N+2.
31:30 PRI_N3 Priority of interrupt number N+3.
Table 5-4. Interrupt Enable/Disable Registers
Register Operation Bit Value Comment
Interrupt Set
Enable Register
(CM0_ISER)
Write
1 To enable the interrupt
0 No effect
Read
1 Interrupt is enabled
0 Interrupt is disabled
Interrupt Clear
Enable Register
(CM0_ICER)
Write
1 To disable the interrupt
0 No effect
Read
1 Interrupt is enabled
0 Interrupt is disabled
Table 5-5. Exception States
Exception State Meaning
Inactive
The exception is not active or pending.
Either the exception is disabled or the
enabled exception has not been triggered.
Pending
The exception request is received by the
CPU/NVIC and the exception is waiting to
be serviced by the CPU.
Active
An exception that is being serviced by the
CPU but whose exception handler execu-
tion is not yet complete. A high-priority
exception can interrupt the execution of
lower priority exception. In this case, both
the exceptions are in the active state.
Active and Pending
The exception is serviced by the processor
and there is a pending request from the
same source during its exception handler
execution.
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