PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 77
13. Reset System
PSoC
®
4 supports several types of resets that guarantee error-free operation during power up and allow the device to reset
based on user-supplied external hardware or internal software reset signals. PSoC 4 also contains hardware to enable the
detection of certain resets.
The reset system has these sources:
■ Power-on reset (POR) to hold the device in reset while the power supply ramps up
■ Brownout reset (BOD) to reset the device if the power supply falls below specifications during operation
■ Watchdog reset (WRES) to reset the device if firmware execution fails to service the watchdog timer
■ Software initiated reset (SRES) to reset the device on demand using firmware
■ External reset (XRES) to reset the device using an external electrical signal
■ Protection fault reset (PROT_FAULT) to reset the device if unauthorized operating conditions occur
13.1 Reset Sources
The following sections provide a description of the reset sources available in PSoC 4.
13.1.1 Power-on Reset
Power-on reset is provided for system reset at power-up. POR holds the device in reset until the supply voltage, V
DDD
, is
according to the datasheet specification. The POR activates automatically at power-up.
POR events do not set a reset cause status bit, but can be partially inferred by the absence of any other reset source. If no
other reset event is detected, then the reset is caused by POR, BOD, or XRES.
13.1.2 Brownout Reset
Brownout reset monitors the chip digital voltage supply V
CCD
and generates a reset if V
CCD
is below the minimum logic oper-
ating voltage specified in the device datasheet. BOD is available in all power modes.
BOD events do not set a reset cause status bit, but in some cases they can be detected. In some BOD events, V
CCD
will fall
below the minimum logic operating voltage, but remain above the minimum logic retention voltage. Thus, some BOD events
may be distinguished from POR events by checking for logic retention.
13.1.3 Watchdog Reset
Watchdog reset (WRES) detects errant code by causing a reset if the watchdog timer is not cleared within the user-specified
time limit. This feature is enabled by default. It can be disabled by writing '0xACED8865' to the WDT_DISABLE_KEY register.
The RESET_WDT status bit of the RES_CAUSE register is set when a watchdog reset occurs. This bit remains set until
cleared or until a POR, XRES, or BOD reset; for example, in the case of a device power cycle. All other resets leave this bit
untouched.
For more details, see the Watchdog Timer chapter on page 73.
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