Cypress PSoC 4000 Series - HFCLK Predivider Configuration; SYSCLK Prescaler Configuration; Peripheral Clock Divider Configuration

58 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Clocking System
8.3.2 HFCLK Predivider Configuration
The HFCLK predivider allows the device to divide the HFCLK selection mux input before use as HFCLK. The predivider is
capable of dividing the HFCLK by powers of 2 between 1 and 8. The predivider value is set using register CLK_SELECT bits
HFCLK_DIV, as described in Table 8-3. The HFCLK predivider is set to a divide value of 4 during boot to reduce current con-
sumption.
Note HFCLK's frequency cannot exceed 16 MHz.
8.3.3 SYSCLK Prescaler Configuration
The SYSCLK Prescaler allows the device to divide the HFCLK before use as SYSCLK, which allows for non-integer relation-
ships between peripheral clocks and the system clock. SYSCLK must be equal to or faster than all other clocks in the device
that are derived from HFCLK. The SYSCLK prescaler is capable of dividing the HFCLK by1, 2, 4, or 8. The prescaler divide
value is set using register CLK_SELECT bits SYSCLK_DIV, as described in Table 8-4. The prescaler is initially configured to
divide by 1.
Note The SYSCLK frequency cannot exceed 16 MHz.
8.3.4 Peripheral Clock Divider Configuration
The four peripheral clocks are derived from the HFCLK using the 16-bit peripheral clock dividers. Each is capable of dividing
the input clock by values between 1 and 65,536. Each of the four dividers is controlled by a PERI_DIV_16_CTL register,
whose mapping is explained in Table 8-5.
The PERI_DIV_CMD register can be used to enable, disable, and select the type of clock dividers for all peripheral clock
dividers. See the PERI_DIV_CMD in the PSoC 4000 Family: PSoC 4 Registers TRM for more details.
Table 8-3. HFCLK Predivider Value Bits HFCLK_DIV
Name Description
HFCLK_DIV[1:0]
HFCLK predivider value
0: No divider on HFCLK
1: Divides HFCLK by 2
2: Divides HFCLK by 4
3: Divides HFCLK by 8
Table 8-4. SYSCLK Prescaler Divide Value Bits SYSCLK_DIV
Name Description
SYSCLK_DIV[1:0]
SYSCLK prescaler divide value
0: SYSCLK = HFCLK
1: SYSCLK = HFCLK/2
2: SYSCLK = HFCLK/4
3: SYSCLK = HFCLK/8
Table 8-5. Peripheral Clock Divider Control Register PERI_DIV_16_CTLx
Bits Name Description
0EN
Enables or disables the divider
0: Divider disabled
1: Divider enabled
23:8 INT16_DIV
Divide value for the divider. Output = Input/(INT16_DIV + 1)
Acceptable divide values range from 0 to 65,536.