PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 65
Power Supply and Monitoring
a high-power supply rejection ratio. The Quiet regulator is
available only in Active and Sleep power modes.
9.3.1.3 Deep-Sleep Regulator
This regulator supplies the circuits that remain powered in
Deep-Sleep mode, such as the ILO and SCB. The Deep-
Sleep regulator is available in all power modes. In Active
and Sleep power modes, the main output of this regulator is
connected to the output of the Active digital regulator
(V
CCD
). This regulator also has a separate replica output
that provides a stable voltage for the ILO. This output is not
connected to V
CCD
in Active and Sleep modes.
9.4 Voltage Monitoring
The voltage monitoring system includes power-on-reset
(POR) and brownout detection (BOD).
9.4.1 Power-On-Reset (POR)
POR circuits provide a reset pulse during the initial power
ramp. POR circuits monitor V
CCD
voltage. Typically, the
POR circuits are not very accurate with respect to trip-point.
POR circuits are used during initial chip power-up and then
disabled.
9.4.1.1 Brownout-Detect (BOD)
The BOD circuit protects the operating or retaining logic
from possibly unsafe supply conditions by applying reset to
the device. BOD circuit monitors the V
CCD
voltage. The
BOD circuit generates a reset if a voltage excursion dips
below the minimum V
CCD
voltage required for safe opera-
tion (see the device datasheet for details). The system will
not come out of RESET until the supply is detected to be
valid again.
To ensure reliable operation of the device, the watchdog
timer should be used in all designs. Watchdog timer pro-
vides protection against abnormal brownout conditions that
may compromise the CPU functionality. See Watchdog
Timer chapter on page 73 for more details.
9.5 Register List
Table 9-2. Power Supply and Monitoring Register List
Register Name Description
PWR_CONTROL
Power Mode Control Register – This register allows configuration of device power modes and regulator
activity.
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