Cypress PSoC 4000 Series - Peripheral Connections; Firmware Controlled GPIO; Capsense; Timer, Counter, and Pulse Width Modulator (TCPWM) Block

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 53
I/O System
7.8 Peripheral Connections
7.8.1 Firmware Controlled GPIO
See Table 7-3 to know the HSIOM settings for a firmware
controlled GPIO. GPIO_PRTx_DR is the data register used
to read and write the output data for the GPIOs. A write
operation to this register changes the GPIO output to the
written value. Note that a read operation reflects the output
data written to this register and not the current state of the
GPIOs. Using this register, read-modify-write sequences
can be safely performed on a port that has both input and
output GPIOs.
In addition to the data register, three other registers –
GPIO_PRTx_DR_SET, GPIO_PRTx_DR_CLR, and
GPIO_PRTx_INV – are provided to set, clear, and invert the
output data respectively of a specific pin in a port without
affecting other pins. Writing ‘1’ into these registers will set,
clear, or invert; writing ‘0’ will have no affect on the pin sta-
tus.
GPIO_PRTx_PS is the I/O pad register that provides the
state of the GPIOs when read. Writes to this register have
no effect.
7.8.2 CapSense
The pins that support CSD can be configured as CapSense
widgets such as buttons, slider elements, touchpad ele-
ments, or proximity sensors. CapSense also requires exter-
nal tank capacitors and shield lines. Table 7-8 shows the
GPIO and HSIOM settings required for CapSense. See the
CapSense chapter on page 127 for more information.
7.8.3 Timer, Counter, and Pulse Width Modulator (TCPWM) Block
TCPWM has dedicated connections to the pin. See the device datasheet for details on these dedicated pins of PSoC 4. Note
that when the TCPWM block inputs such as start and stop are taken from the pins, the drive mode can be only high-z digital
because the TCPWM block disables the output buffer at the input pins.
7.9 Registers
Note The 'x' in the GPIO register name denotes the port number. For example, GPIO_PTR1_DR is the Port 1 output data
register.
Table 7-8. CapSense Settings
CapSense Pin
GPIO Drive Mode
(GPIO_PRTx_PC)
Digital Input Buffer Setting
(GPIO_PRTx_PC2)
HSIOM Setting
Sensor High-Impedance Analog Disable Buffer CSD_SENSE
Shield High-Impedance Analog Disable Buffer CSD_SHIELD
CMOD (normal operation) High-Impedance Analog Disable Buffer AMUXBUS A or CSD_COMP
CMOD (GPIO precharge, only available in select
GPIO)
High-Impedance Analog Disable Buffer AMUXBUS B or CSD_COMP
CSH TANK (GPIO precharge, only available in
select GPIO)
High-Impedance Analog Disable Buffer AMUXBUS B or CSD_COMP
Table 7-9. I/O Registers
Name Description
GPIO_PRTx_DR Port Output Data Register
GPIO_PRTx_DR_SET Port Output Data Set Register
GPIO_PRTx_DR_CLR Port Output Data Clear Register
GPIO_PRTx_DR_INV Port Output Data Inverting Register
GPIO_PRTx_PS Port Pin State Register - Reads the logical pin state of I/O
GPIO_PRTx_PC Port Configuration Register - Configures the output drive mode, input threshold, and slew rate
GPIO_PRTx_PC2 Port Secondary Configuration Register - Configures the input buffer of I/O pin
GPIO_PRTx_INTR_CFG Port Interrupt Configuration Register
GPIO_PRTx_INTR Port Interrupt Status Register
HSIOM_PORT_SELx HSIOM Port Selection Register