Cypress PSoC 4000 Series - 6. Memory Map; 6.1 Features

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 41
6. Memory Map
All PSoC
®
4 memory (flash, SRAM, and SROM) and all registers are accessible by the CPU and in most cases by the debug
system. This chapter contains an overall map of the addresses of the memories and registers.
6.1 Features
The PSoC 4 memory system has the following features:
■ 16K bytes flash, 2K bytes SRAM
■ 4K byte SROM contains boot and configuration routines
■ ARM Cortex-M0 32-bit linear address space, with regions for code, SRAM, peripherals, and CPU internal registers
■ Flash is mapped to the Cortex-M0 code region
■ SRAM is mapped to the Cortex-M0 SRAM region
■ Peripheral registers are mapped to the Cortex-M0 peripheral region
■ The Cortex-M0 Private Peripheral Bus (PPB) region includes registers implemented in the CPU core. These include reg-
isters for NVIC, SysTick timer, and fixed-function I2C block. For more information, see the Cortex-M0 CPU chapter on
page 25.
6.2 How It Works
The PSoC 4 memory map is detailed in the following tables. For additional information, refer to the PSoC 4000 Family: PSoC
4 Registers TRM.
The ARM Cortex-M0 has a fixed address map allowing access to memory and peripherals using simple memory access
instructions. The 32-bit (4 GB) address space is divided into the regions shown in Table 6-1. Note that code can be executed
from the code and SRAM regions.
Table 6-1. Cortex-M0 Address Map
Address Range Name Use
0x00000000 – 0x1FFFFFFF Code
Executable region for program code. You can also put data here. Includes the exception
vector table, which starts at address 0.
0x20000000 – 0x3FFFFFFF SRAM Executable region for data. You can also put code here.
0x40000000 – 0x5FFFFFFF Peripheral All peripheral registers. Code cannot be executed out of this region.
0x60000000 – 0xDFFFFFFF – Not used
0xE0000000 – 0xE00FFFFF PPB Peripheral registers within the CPU core.
0xE0100000 – 0xFFFFFFFF Device PSoC 4 implementation-specific.