PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 89
Inter-Integrated Circuit (I2C)
15.2.6.2 Configuring for EZI2C Mode
To configure the I2C block for EZI2C mode, set the following I2C register bits
1. Select the EZI2C mode by writing '1' to the EZ_MODE bit (bit 10) of the SCB_CTRL register.
2. Follow steps 2 to 4 mentioned in Configuring for EZI2C Mode.
3. Set the S_READY_ADDR_ACK (bit 12) and S_READY_DATA_ACK (bit 13) bits of the SCB_I2C_CTRL register.
15.2.7 Internal and External Clock Operation in I2C
The I2C block supports both internally and externally clocked operation for data-rate generation. Internally clocked operations
use a clock signal derived from the PSoC system bus clock. Externally clocked operations use a clock provided by the user.
Externally clocked operation allows limited functionality in the Deep-Sleep power mode, in which on-chip clocks are not
active. For more information on system clocking, see the Clocking System chapter on page 61.
Externally clocked operation is limited to the following cases:
■ Slave functionality.
■ EZ functionality.
TX and RX FIFOs do not support externally clocked operation; therefore, it is not used for non-EZ functionality.
Internally and externally clocked operations are determined by two register fields of the SCB_CTRL register:
Table 15-6. SCB_TX_CTRL/SCB_RX_CTRL Register
Bits Name Description
[3:0] DATA_ WIDTH
'DATA_WIDTH + 1' is the number of bits in the transmitted or received data
frame. This is always 7.
8 MSB_FIRST
1= MSB first (this should always be true)
0= LSB first
9MEDIAN
This is for SCB_RX_CTRL only.
Decides whether a digital three-tap median filter is applied on the input interface
lines. This filter should reduce susceptibility to errors, but it requires higher overs-
ampling values.
1=Enabled
0=Disabled
Table 15-7. SCB_TX_FIFO_CTRL/SCB_RX_FIFO_CTRL
Bits Name Description
[3:0] TRIGGER_LEVEL
Trigger level. When the transmitter FIFO has less entries or the receiver FIFO
has more entries than the value of this field, a transmitter or receiver trigger event
is generated in the respective case.
16 CLEAR When '1', the transmitter or receiver FIFO and the shift registers are cleared.
17 FREEZE
When '1', hardware reads/writes to the transmitter or receiver FIFO have no
effect. Freeze does not advance the TX or RX FIFO read/write pointer.
Table 15-8. SCB_CTRL Registers
Bits Name Value Description
[25:24] MODE
00 I2C mode
01 Reserved
10 Reserved
11 Reserved
31 ENABLED
0 I2C block disabled
1 I2C block enabled
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