PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 141
Program and Debug Interface
b. The data parity bit indicates the parity of the data
read or written. It is an even parity; this means when
XORed with the data bits, the result will be 0.
If the parity bit indicates a data error, corrective
action should be taken. For a read packet, if the host
detects a parity error, it must abort the programming
operation and restart. For a write packet, if the target
detects a parity error, it generates a FAULT ACK
response in the next packet.
According to the SWD protocol, the host can generate any
number of SWDCK clock cycles between two packets with
SWDIO low. It is recommended to generate three or more
dummy clock cycles between two SWD packets if the clock
is not free-running or to make the clock free-running in IDLE
mode.
The SWD interface can be reset by clocking the SWDCK
line for 50 or more cycles with SWDIO high. To return to the
idle state, clock the SWDIO low once.
18.3.1 SWD Timing Details
The SWDIO line is written to and read at different times
depending on the direction of communication. The host
drives the SWDIO line during the Host Packet Request
Phase and, if the host is writing data to the target, during the
Data Transfer phase as well. When the host is driving the
SWDIO line, each new bit is written by the host on falling
SWDCK edges, and read by the target on rising SWDCK
edges. The target drives the SWDIO line during the Target
Acknowledge Response Phase and, if the target is reading
out data, during the Data Transfer Phase as well. When the
target is driving the SWDIO line, each new bit is written by
the target on rising SWDCK edges, and read by the host on
falling SWDCK edges.
Table 18-1 and Figure 18-2 illustrate the timing of SWDIO bit
writes and reads.
18.3.2 ACK Details
The acknowledge (ACK) bit-field is used to communicate
the status of the previous transfer. OK ACK means that pre-
vious packet was successful. A WAIT response requires a
data phase. For a FAULT status, the programming operation
should be aborted immediately. Table 18-2 shows the ACK
bit-field decoding details.
Details on WAIT and FAULT response behaviors are as fol-
lows:
■ For a WAIT response, if the transaction is a read, the
host should ignore the data read in the data phase. The
target does not drive the line and the host must not
check the parity bit as well.
■ For a WAIT response, if the transaction is a write, the
data phase is ignored by the PSoC 4. But, the host must
still send the data to be written to complete the packet.
The parity bit corresponding to the data should also be
sent by the host.
■ For a WAIT response, it means that the PSoC 4 is pro-
cessing the previous transaction. The host can try for a
maximum of four continuous WAIT responses to see if
an OK response is received. If it fails, then the program-
ming operation should be aborted and retried again.
■ For a FAULT response, the programming operation
should be aborted and retried again by doing a device
reset.
18.3.3 Turnaround (Trn) Period Details
There is a turnaround period between the packet request
and the ACK phases, as well as between the ACK and the
data phases for host write transfers, as shown in
Figure 18-2. According to the SWD protocol, the Trn period
is used by both the host and target to change the drive
modes on their respective SWDIO lines. During the first Trn
period after the packet request, the target starts driving the
ACK data on the SWDIO line on the rising edge of SWDCK.
This action ensures that the host can read the ACK data on
the next falling edge. Thus, the first Trn period lasts only
one-half cycle. The second Trn period of the SWD packet is
one and a half cycles. Neither the host nor the PSoC 4
should drive the SWDIO line during the Trn period.
Table 18-1. SWDIO Bit Write and Read Timing
SWD Packet Phase
SWDIO Edge
Falling Rising
Host Packet Request
Host Write Target Read
Host Data Transfer
Target Ack Response
Host Read Target Write
Target Data Transfer
Table 18-2. SWD Transfer ACK Response Decoding
Response ACK[2:0]
OK 3b001
WAIT 3b010
FAULT 3b100
NO ACK 3b111
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