PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 33
Interrupts
5.3.3 Exception Vector Table
The exception vector table (Table 5-1), stores the entry point addresses for all exception handlers. The CPU fetches the
appropriate address based on the exception number.
In Table 5-1, the first word (4 bytes) is not marked as excep-
tion number zero. This is because the first word in the
exception table is used to initialize the main stack pointer
(MSP) value on device reset; it is not considered as an
exception. In PSoC 4, the vector table can be configured to
be located either in flash memory (base address of
0x00000000) or SRAM (base address of 0x20000000). This
configuration is done by writing to the VECT_IN_RAM bit
field (bit 0) in the CPUSS_CONFIG register. When the
VECT_IN_RAM bit field is ‘1’, CPU fetches exception han-
dler addresses from the SRAM vector table location. When
this bit field is ‘0’ (reset state), the vector table in flash mem-
ory is used for exception address fetches. You must set the
VECT_IN_RAM bit field as part of the device boot code to
configure the vector table to be in SRAM. The advantage of
moving the vector table to SRAM is that the exception han-
dler addresses can be dynamically changed by modifying
the SRAM vector table contents. However, the nonvolatile
flash memory vector table must be modified by a flash mem-
ory write.
Reads of flash addresses 0x00000000 and 0x00000004 are
redirected to the first eight bytes of SROM to fetch the stack
pointer and reset vectors, unless the NO_RST_OVR bit of
the CPUSS_SYSREQ register is set. To allow flash read
from addresses 0x00000000 and 0x00000004, the
NO_RST_OVR bit should be set to ‘1’. The stack pointer
vector holds the address that the stack pointer is loaded with
on reset. The reset vector holds the address of the boot
sequence. This mapping is done to use the default
addresses for the stack pointer and reset vector from SROM
when the device reset is released. For reset, boot code in
SROM is executed first and then the CPU jumps to address
0x00000004 in flash to execute the handler in flash. The
reset exception address in the SRAM vector table is never
used because VECT_IN_RAM is 0 on reset.
Also, when the SYSREQ bit of the CPUSS_SYSREQ regis-
ter is set, reads of flash address 0x00000008 are redirected
to SROM to fetch the NMI vector address instead of from
flash. Reset CPUSS_SYSREQ to read the flash at address
0x00000008.
The exception sources (exception numbers 1 to 15) are
explained in 5.4 Exception Sources. The exceptions marked
as Reserved in Table 5-1 are not used, although they have
addresses reserved for them in the vector table. The inter-
rupt sources (exception numbers 16 to 24) are explained in
5.5 Interrupt Sources.
5.4 Exception Sources
This section explains the different exception sources listed
in Table 5-1 (exception numbers 1 to 15).
5.4.1 Reset Exception
Device reset is treated as an exception in PSoC 4. It is
always enabled with a fixed priority of –3, the highest priority
exception. A device reset can occur due to multiple reasons,
such as power-on-reset (POR), external reset signal on
XRES pin, or watchdog reset. When the device is reset, the
initial boot code for configuring the device is executed out of
supervisory read-only memory (SROM). The boot code and
other data in SROM memory are programmed by Cypress,
and are not read/write accessible to external users. After
completing the SROM boot sequence, the CPU code execu-
tion jumps to flash memory. Flash memory address
0x00000004 (Exception#1 in Table 5-1) stores the location
Table 5-1. Exception Vector Table
Exception Number Exception Exception Priority Vector Address
– Initial Stack Pointer Value Not applicable (NA)
Base_Address - 0x00000000 (start of flash memory) or
0x20000000 (start of SRAM)
1 Reset –3, the highest priority Base_Address + 0x04
2 Non Maskable Interrupt (NMI) –2 Base_Address + 0x08
3 HardFault –1 Base_Address + 0x0C
4-10 Reserved NA Base_Address + 0x10 to Base_Address + 0x28
11 Supervisory Call (SVCall) Configurable (0 - 3) Base_Address + 0x2C
12-13 Reserved NA Base_Address + 0x30 to Base_Address + 0x34
14 PendSupervisory (PendSV) Configurable (0 - 3) Base_Address + 0x38
15 System Timer (SysTick) Configurable (0 - 3) Base_Address + 0x3C
16 External Interrupt(IRQ0) Configurable (0 - 3) Base_Address + 0x40
… … Configurable (0 - 3) …
24 External Interrupt(IRQ8) Configurable (0 - 3) Base_Address + 0x52
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