PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 27
Cortex-M0 CPU
4.5 Registers
The Cortex-M0 has 16 32-bit registers, as Table 4-2 shows:
■ R0 to R12 – General-purpose registers. R0 to R7 can be accessed by all instructions; the other registers can be accessed
by a subset of the instructions.
■ R13 – Stack pointer (SP). There are two stack pointers, with only one available at a time. In thread mode, the CONTROL
register indicates the stack pointer to use, Main Stack Pointer (MSP) or Process Stack Pointer (PSP).
■ R14 – Link register. Stores the return program counter during function calls.
■ R15 – Program counter. This register can be written to control program flow.
Table 4-3 shows how the PSR bits are assigned.
Table 4-2. Cortex-M0 Registers
Name
Type
a
Reset Value Description
R0-R12 RW Undefined R0-R12 are 32-bit general-purpose registers for data operations.
MSP (R13)
PSP (R13)
RW [0x00000000]
The stack pointer (SP) is register R13. In thread mode, bit[1] of the CONTROL register
indicates which stack pointer to use:
0 = Main stack pointer (MSP). This is the reset value.
1 = Process stack pointer (PSP).
On reset, the processor loads the MSP with the value from address 0x00000000.
LR (R14) RW Undefined
The link register (LR) is register R14. It stores the return information for subroutines,
function calls, and exceptions.
PC (R15) RW [0x00000004]
The program counter (PC) is register R15. It contains the current program address. On
reset, the processor loads the PC with the value from address 0x00000004. Bit[0] of the
value is loaded into the EPSR T-bit at reset and must be 1.
PSR RW Undefined
The program status register (PSR) combines:
Application Program Status Register (APSR).
Execution Program Status Register (EPSR).
Interrupt Program Status Register (IPSR).
APSR RW Undefined
The APSR contains the current state of the condition flags from previous instruction
executions.
EPSR RO [0x00000004].0 On reset, EPSR is loaded with the value bit[0] of the register [0x00000004].
IPSR RO 0 The IPSR contains the exception number of the current ISR.
PRIMASK RW 0 The PRIMASK register prevents activation of all exceptions with configurable priority.
CONTROL RW 0 The CONTROL register controls the stack used when the processor is in thread mode.
a. Describes access type during program execution in thread mode and handler mode. Debug access can differ.
Table 4-3. Cortex-M0 PSR Bit Assignments
Bit PSR Register Name Usage
31 APSR N Negative flag
30 APSR Z Zero flag
29 APSR C Carry or borrow flag
28 APSR V Overflow flag
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