Cypress PSoC 4000 Series - Digital Input Buffer

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 47
I/O System
Figure 7-2. I/O Cell Architecture in PSoC 4000
7.3.1 Digital Input Buffer
The digital input buffer provides a high-impedance buffer for
the external digital input. The buffer is enabled and disabled
by the INP_DIS bit of the Port Configuration Register 2
(GPIO_PRTx_PC2, where x is the port number). The buffer
is configurable for the following modes:
■ CMOS
■ LVTTL
Digital
Logic
Slew
Control
PORT_SLOW (GPIO_PRTx_PC[25])
GPIO_PRTx_PC[3y+2:3y]
In
OE
PIN
VDD/VDDIO
VDD/VDDIO
Digital Output Path
GPIO_PRTx_DR[y]
ACTIVE_0 (TCPWM)
ACTIVE_1 (TCPWM)
ACTIVE_2 (TCPWM)
ACTIVE_3 (CSD Comparator)
DEEP_SLEEP_1 (SWD)
DEEP_SLEEP_0 (I2C)
OUTPUT ENABLE
HSIOM_PORT_SELx[4y+3:4y]
Pin Interrupt Signal
DATA
(GPIO_PRTx_INTR[y])
EDGE_SEL
(GPIO_PRTx_INTR_CFG[2y+1:2y])
I2C
DATA (GPIO_PRTx_PS[y])
INP_DIS (GPIO_PRTx_PC2[y])
Digital Input Path
Switches
HSIOM_PORT_SELx[4y+3:4y]
AMUXBUS-A (CapSense Source)
AMUXBUS-B (CapSense Shield)
Analog
HSIOM
3
4
Input Buffer
Disable
Drive
Mode
DSI
HSIOM
PORT_VTRIP_SEL (GPIO_PRTx_PC[24])
Buffer Mode Select
--------------------------
CMOS
LVTTL
HSIOM_PORT_SELx[4y+3:4y]
4
IO CELL
Input Buffer
Output Driver
4
x – Port Number
y – Pin Number
VSS
VSS VSS
GPIO
Edge
Detect