112 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Timer, Counter, and PWM
16.3.3 Quadrature Decoder Mode
Quadrature decoders are used to determine speed and position of a rotary device (such as servo motors, volume control
wheels, and PC mice). The quadrature encoder signals are used as phiA and phiB inputs to the decoder.
16.3.3.1 Block Diagram
Figure 16-8. Quadrature Mode Block Diagram
16.3.3.2 How It Works
Quadrature decoding only runs on counter_clock. It can
operate in three sub-modes: X1, X2, and X4 modes. These
encoding modes can be controlled by the
QUADRATURE_MODE[21:20] field of the counter control
register (TCPWM_CNT_CTRL). This mode uses double
buffered capture registers.
The Quadrature mode operation occurs as follows:
■ Quadrature phases phiA and phiB: Counting direction is
determined by the phase relationship between phiA and
phiB. These phases are connected to the count and the
start trigger inputs, respectively as hardware input to the
decoder.
■ Quadrature index signal: This is connected to the reload
signal as a hardware input. This event generates a TC
condition, as shown in Figure 16-9.
On TC, the counter is set to 0x0000 (in the up counting
mode) or to the period value (in the down counting
mode).
Note The down counting mode is recommended to be
used with a period value of 0x8000 (the mid-point value).
■ A pulse on CC output signal is generated when the count
register value reaches 0x0000 or 0xFFFF. On a CC con-
dition, the count register is set to the period value
(0x8000 in this case).
■ On TC or CC condition:
❐ Count register value is copied to the capture register
❐ Capture register value is copied to the buffer capture
register
❐ This condition can be used to generate an interrupt
request
■ The value in the capture register can be used to deter-
mine which condition caused the event and whether:
❐ A counter underflow occurred (value 0)
❐ A counter overflow occurred (value 0xFFFF)
❐ An index/TC event occurred (value is not equal to
either 0 or 0xFFFF)
■ The DOWN bit field of counter status
(TCPWM_CNTx_STATUS) register can be read to deter-
mine the current counting direction. Value '0' indicates a
previous increment operation and value '1' indicates pre-
vious decrement operation. Figure 16-9 illustrates
quadrature behavior in the X1 encoding mode.
❐ A positive edge on phiA increments the counter
when phiB is '0' and decrements the counter when
phiB is '1'.
❐ The count register is initialized with the period value
on an index/reload event.
❐ Terminal count is generated when the counter is ini-
tialized by index event. This event can be used to
generate an interrupt.
❐ When the count register reaches 0xFFFF (the maxi-
mum count register value), the count register value is
copied to the capture register and the count register
is initialized with period value (0x8000 in this case).
PERIOD
COUNTER
CAPTURE
BUFFER CAPTURE
==
index
phiA
Stop
phiB
CC
TC
counter_clock
0x0000
0xFFFF
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