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Cypress PSoC 4000 Series - Page 113

Cypress PSoC 4000 Series
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PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 113
Timer, Counter, and PWM
Figure 16-9. Timing Diagram for Quadrature Mode, X1 Encoding
The quadrature phases are detected on the counter_clock. Within a single counter_clock period, the phases should not
change value more than once. The X2 and X4 quadrature encoding modes count twice and four times as fast as the X1
encoding mode.
Figure 16-10 illustrates the quadrature mode behavior in the X2 and X4 encoding modes.
Period
TC
CC
Quadrature, X1 encoding
0x8000
Y 0xFFFF
capture
buffer capture
X
Y
0x8000
0x8001
0x8002
0x8000
0x7FFF
counter
phiA
phiB
index/reload
event
0x8003
counter_clock
0xFFFF

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