114 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Timer, Counter, and PWM
Figure 16-10. Timing Diagram for Quadrature Mode, X2 and X4 Encoding
16.3.3.3 Configuring Counter for Quadrature Mode
The steps to configure the counter for quadrature mode of operation and the affected register bits are as follows.
1. Disable the counter by writing '0' to the COUNTER_ENABLED field of the TCPWM_CTRL register.
2. Select Quadrature mode by writing '011' to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
3. Set the required 16-bit period in the TCPWM_CNT_PERIOD register.
4. Set the required encoding mode by writing to the QUADRATURE_MODE[21:20] field of the TCPWM_CNT_CTRL register.
5. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Index and Stop).
6. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Index and Stop).
7. If required, set the interrupt upon TC or CC condition, as shown in “Interrupts” on page 104.
8. Enable the counter by writing '1' to the COUNTER_ENABLED field of the TCPWM_CTRL register.
Period
TC
Quadrature, X2 encoding
4
counter
phiA
phiB
index/reload
event
counter_clock
4
5
67 8 7 6
Period
TC
Quadrature, X4 encoding
4
counter
phiA
phiB
index/reload
event
counter_clock
4 567891011 12 11109 8
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