PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 63
Power Supply and Monitoring
9.2 Power Supply Scenarios
The following diagrams illustrate the different ways in which the device is powered.
9.2.1 Single 1.8 V to 5.5 V Unregulated Supply
If a 1.8-V to 5.5-V supply is to be used as the unregulated power supply input, it should be connected as shown in Figure 9-2.
Figure 9-2. Single Regulated V
DD
Supply
In this mode, the device is powered by an external power supply that can be anywhere in the range of 1.8 V to 5.5 V. This
range is also designed for battery-powered operation; for instance, the chip can be powered from a battery system that starts
at 3.5 V and works down to 1.8 V. In this mode, the internal regulator supplies the internal logic. The V
CCD
output must be
bypassed to ground via a 0.1 µF external ceramic capacitor.
Bypass capacitors are also required from V
DDD
to ground; typical practice for systems in this frequency range is to use a bulk
capacitor in the 1 µF to 10 µF range in parallel with a smaller ceramic capacitor (0.1 µF, for example). Note that these are sim-
ply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic
should be simulated to design and obtain optimal bypassing.
9.2.2 Direct 1.71 V to 1.89 V Regulated Supply
In direct supply configuration, V
CCD
and V
DD
are shorted together and connected to a 1.71-V to 1.89-V supply. This regulated
supply should be connected to the device, as shown in Figure 9-3.
PSoC 4
V
DDD
V
CCD
V
SS
0.1 uF
1 uF
0.1 uF
1.8 V - 5.5 V
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