PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 75
Watchdog Timer
12.3.2 WDT Interrupts and Low-Power Modes
The watchdog counter can send interrupt requests to the CPU in Active power mode and to the WakeUp Interrupt Controller
(WIC) in Sleep and Deep-Sleep power modes. It works as follows:
■ Active Mode: In Active power mode, the WDT can send the interrupt to the CPU. The CPU acknowledges the interrupt
request and executes the ISR. The interrupt must be cleared after entering the ISR in firmware.
■ Sleep or Deep-Sleep Mode: In this mode, the CPU subsystem is powered down. Therefore, the interrupt request from
the WDT is directly sent to the WIC, which will then wake up the CPU. The CPU acknowledges the interrupt request and
executes the ISR. The interrupt must be cleared after entering the ISR in firmware.
For more details on device power modes, see the Power Modes chapter on page 69.
12.3.3 WDT Reset Mode
The RESET_WDT bit in the RES_CAUSE register indicates the reset generated by the WDT. This bit remains set until
cleared or until a power-on reset (POR), brownout reset (BOD), or external reset (XRES) occurs. All other resets leave this bit
untouched. For more details, see the Reset System chapter on page 77.
12.4 Register List
Table 12-1. WDT Registers
Register Name Description
WDT_DISABLE_KEY Disables the WDT when 0XACED8865 is written, for any other value WDT works normally
WDT_COUNTER Provides the count value of the WDT
WDT_MATCH Stores the match value of the WDT
SRSS_INTR Services the WDT to avoid reset
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