PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 51
I/O System
7.4 High-Speed I/O Matrix
The high-speed I/O matrix (HSIOM) is a group of high-speed switches that routes GPIOs to the peripherals inside the device.
As the GPIOs are shared for multiple functions, HSIOM multiplexes the pin and connects to a particular peripheral selected
by the user. The HSIOM_PORT_SELx register is provided to select the peripheral. It is a 32-bit wide register available for
each port, with each pin occupying four bits. This register provides up to 16 different options for a pin as listed in Table 7-3.
Note The Active and Deep-Sleep sources are pin dependent. See the “Pinouts” section of the device datasheet for more
details on the features supported by each pin.
7.5 I/O State on Power Up
During power up all the GPIOs are in high-impedance analog state and the input buffers are disabled. During run time, GPIOs
can be configured by writing to the associated registers. Note that the pins supporting debug access port (DAP) connections
(SWD lines) are always enabled as SWD lines during power up. However, the DAP connection can be disabled or reconfig-
ured for general-purpose use through HSIOM. However, this reconfiguration takes place only after the device boots and start
executing code.
7.6 Behavior in Low-Power Modes
Table 7-4 shows the status of GPIOs in low-power modes.
7.7 Interrupt
In the PSoC 4 device, all the port pins have the capability to generate interrupts. As shown in Figure 7-2, the pin signal is
routed to the interrupt controller through the GPIO Edge Detect block.
Table 7-3. PSoC 4000 HSIOM Port Settings
HSIOM_PORT_SELx ('x' denotes port number and 'y' denotes pin number)
Bits Name (SEL 'y') Value Description (Selects pin 'y' source (0 y 7)
4y+3 : 4y
DR 0 Pin is firmware-controlled GPIO.
CSD_SENSE 4 Pin is a CSD sense pin (analog mode).
CSD_SHIELD 5 Pin is a CSD shield pin (analog mode).
AMUXA 6 Pin is connected to AMUXBUS-A.
AMUXB 7
Pin is connected to AMUXBUS-B. This mode is also used for GPIO pre-charging of
tank capacitors.
ACTIVE_0 8 Pin-specific Active source # 0 (TCPWM, EXT_CLK).
ACTIVE_1 9 Pin-specific Active source #1 (TCPWM).
ACTIVE_2 10 Pin-specific Active source #2 (TCPWM).
ACTIVE_3 11 Pin-specific Active source #3 (CSD comparator).
DEEP_SLEEP_0 14 Pin-specific Deep-Sleep source #0 (SCB - I
2
C).
DEEP_SLEEP_1 15 Pin-specific Deep-Sleep source #1 (SWD).
Table 7-4. GPIO in Low-Power Modes
Low-Power Mode Status
Sleep
■ GPIOs are active and can be driven by peripherals such as CapSense, TCPWM, and I
2
C, which can work in
sleep mode.
■ Input buffers are active; thus an interrupt on any I/O can be used to wake up the CPU.
Deep-Sleep
■ GPIO output pin states are latched and remain in the frozen state, except the I
2
C pins. I
2
C block can work in the
deep-sleep mode and can wake up the CPU on address match event.
■ Input buffers are also active in this mode; pin interrupts are functional.
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