Cypress PSoC 4000 Series - 1. Introduction; 1.1 Top Level Architecture

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 13
1. Introduction
PSoC
®
4 is a programmable embedded system controller with an ARM
®
Cortex
®
-M0 CPU.CY8C4000 family is the smallest
member of the PSoC 4 family of devices and is upward-compatible with larger members of PSoC 4.
PSoC 4 devices have these characteristics:
■ High-performance, 32-bit single-cycle Cortex-M0 CPU core
■ Capacitive touch sensing (CapSense
®
)
■ Configurable Timer/Counter/PWM block
■ Configurable I
2
C block with master, slave, and multi-master operating modes
■ Low-power operating modes – Sleep and Deep-Sleep
This document describes each functional block of the PSoC 4000 device in detail. This information will help designers to cre-
ate system-level designs.
1.1 Top Level Architecture
Figure 1-1 shows the major components of the PSoC 4000 architecture.