102 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Timer, Counter, and PWM
The block has these interfaces:
■ Bus interface: Connects the block to the CPU subsystem.
■ I/O signal interface: Connects input triggers (such as reload, start, stop, count, and capture) and output signals (such as
overflow (OV), underflow (UN), and capture/compare (CC)) to dedicated GPIOs.
■ Interrupts: Provides interrupt request signals from the counter, based on terminal count (TC) or CC conditions.
■ System interface: Consists of control signals such as clock and reset from the system resources subsystem.
This TCPWM block can be configured by writing to the TCPWM registers. See “TCPWM Registers” on page 123 for more
information on all registers required for this block.
16.2.1 Enabling and Disabling Counter in TCPWM Block
The counter can be enabled by setting the COUNTER_ENABLED field (bit 0) of the control register TCPWM_CTRL.
Note The counter must be configured before enabling it. If the counter is enabled after being configured, registers are
updated with the new configuration values. Disabling the counter retains the values in the registers until it is enabled again (or
reconfigured).
16.2.2 Clocking
The TCPWM receives the HFCLK through the system interface to synchronize all events in the block. The counter enable sig-
nal (counter_en), which is generated when the counter is enabled, gates the HFCLK to provide a counter-specific clock
(counter_clock). Output triggers (explained later in this chapter) are also synchronized with the HFCLK.
Clock Prescaling: counter_clock can be prescaled, with divider values of 1, 2, 4… 64, 128. This prescaling is done by modi-
fying the GENERIC field of the counter control (TCPWM_CNT_CTRL) register, as shown in Table 16 -1.
Note Clock prescaling cannot be done in quadrature mode and PWM-DT mode.
Table 16-1. Bit-Field Setting to Prescale Counter Clock
GENERIC[10:8] Description
0 Divide by 1
1 Divide by 2
2 Divide by 4
3 Divide by 8
4 Divide by 16
5 Divide by 32
6 Divide by 64
7 Divide by 128
To Next Page
Loading...
