Cypress PSoC 4000 Series - VDDIO Supply; How It Works; Regulator Summary

64 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Power Supply and Monitoring
Figure 9-3. Single Unregulated V
DD
Supply
In this mode, V
CCD
and V
DDD
pins are shorted together and
bypassed. The internal regulator should be disabled in firm-
ware. See 9.3.1.1 Active Digital Regulator on page 64 for
details.
9.2.3 V
DDIO
Supply.
The V
DDIO
pin, available in certain package types, provides
a separate voltage domain for the I2C pins. See the device
datasheet for the power supply connections when V
DDIO
is
present. In applications where V
DDIO
supply is present and
V
DD
is off, make sure that P3[0] and P3[1] are not floating.
9.3 How It Works
The regulators in Figure 9-1 power the various domains of
the device. All the core regulators and digital I/Os draw their
input power from the V
DD
pin supply. Digital I/Os are sup-
plied from V
DD
. The V
DDIO
pin, available in certain package
types, provides a separate voltage domain for the I2C pins.
See the device datasheet for details.
9.3.1 Regulator Summary
The Active digital regulator and Quiet regulator are enabled
during the Active or Sleep power modes. They are turned off
in the Deep-Sleep mode (see Table 9-1 and Figure 9-1).
9.3.1.1 Active Digital Regulator
For external supplies from 1.8 V and 5.5 V, the Active digital
regulator provides the main digital logic in Active and Sleep
modes. This regulator has its output connected to a pin
(V
CCD
) and requires an external decoupling capacitor (1 µF
X5R).
For supplies below 1.8 V, V
CCD
must be supplied directly. In
this case, V
CCD
and V
DD
must be shorted together, as
shown in Figure 9-3.
The Active digital regulator can be disabled by setting the
EXT_VCCD bit in the PWR_CONTROL register. This action
reduces the power consumption in direct supply mode. The
Active digital regulator is available only in Active and Sleep
power modes.
9.3.1.2 Quiet Regulator
In Active and Sleep modes, this regulator supplies analog
circuits such as the bandgap reference and capacitive sens-
ing subsystem, which require a quiet supply, free of digital
switching noise and power supply noise. This regulator has
PSoC 4
V
DDD
V
CCD
V
SS
0.1 uF
1 uF
1.71 V-1.89 V
Table 9-1. Regulator Status in Different Power Modes
Mode
Active
Regulator
Quiet
Regulator
Stop Off Off
Hibernate Off Off
Deep Sleep Off Off
Sleep On On
Active On On