Cypress PSoC 4000 Series - Output Signals

104 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Timer, Counter, and PWM
16.2.4 Output Signals
The TCPWM block generates several output signals, as shown in Figure 16-3.
Figure 16-3. TCPWM Output Signals
16.2.4.1 Signals upon Trigger Conditions
■ Counter generates an internal overflow (OV) condition when counting up and the count register reaches the period value.
■ Counter generates an internal underflow (UN) condition when counting down and the count register reaches zero.
■ The capture/compare (CC) condition is generated by the TCPWM when the counter is running and one of the following
conditions occur:
❐ The counter value equals the compare value.
❐ A capture event occurs - When a capture event occurs, the TCPWM_CNT_COUNTER register value is copied to the
capture register and the capture register value is copied to the buffer capture register.
Note These signals, when they occur, remain at logic high for two cycles of the system clock. For reliable operation, the con-
dition that causes this trigger should be less than a quarter of the HFCLK. For example, if the HFCLK is running at 24 MHz,
the condition causing the trigger should occur at a frequency less than 6 MHz.
16.2.4.2 Interrupts
The TCPWM block provides a dedicated interrupt output signal from the counter. An interrupt can be generated for a TC con-
dition or a CC condition. The exact definition of these conditions is mode-specific. All eight interrupt output signals from the
eight TCPWMs are also OR'ed together to produce a single interrupt output signal.
Four registers are used for interrupt handling in this block, as shown in Table 16 -2.
Table 16-2. Interrupt Register
Interrupt Registers Bits Name Description
TCPWM_CNT_INTR
(Interrupt request register)
0 TC This bit is set to '1', when a terminal count is detected. Write '1' to clear this bit.
1CC_MATCH
This bit is set to ‘1’ when the counter value matches capture/compare register
value. Write '1' to clear this bit.
TCPWM_CNT_INTR_SET
(Interrupt set request register)
0TC
Write '1' to set the corresponding bit in the interrupt request register. When
read, this register reflects the interrupt request register status.
1CC_MATCH
Write '1' to set the corresponding bit in the interrupt request register. When
read, this register reflects the interrupt request register status.
TCPWM_CNT_INTR_MASK
(Interrupt mask register)
0 TC Mask bit for the corresponding TC bit in the interrupt request register.
1 CC_MATCH Mask bit for the corresponding CC_MATCH bit in the interrupt request register.
TCPWM_CNT_INTR_MASKED
(Interrupt masked request register)
0 TC Logical AND of the corresponding TC request and mask bits.
1 CC_MATCH Logical AND of the corresponding CC_MATCH request and mask bits.
TCPWM block
Interrupt
line_out
line_compl_out
Underflow
Overflow
Capture / Compare