Cypress PSoC 4000 Series - Exceptions - Initialization and Configuration; Registers; Associated Documents

38 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Interrupts
5.11 Exceptions – Initialization and Configuration
This section covers the different steps involved in initializing and configuring exceptions in PSoC 4.
1. Configuring the Exception Vector Table Location: The first step in using exceptions is to configure the vector table location
as required – either in flash memory or SRAM. This configuration is done by writing either a ‘1’ (SRAM vector table) or ‘0’
(flash vector table) to the VECT_IN_RAM bit field (bit 0) in the CPUSS_CONFIG register. This register write is done as
part of device initialization code.
It is recommended that the vector table be available in SRAM if the application needs to change the vector addresses
dynamically. If the table is located in flash, then a flash write operation is required to modify the vector table contents.
PSoC Creator IDE uses the vector table in SRAM by default.
2. Configuring Individual Exceptions: The next step is to configure individual exceptions required in an application.
a. Configure the exception or interrupt source; this includes setting up the interrupt generation conditions. The register
configuration depends on the specific exception required.
b. Define the exception handler function and write the address of the function to the exception vector table. Table 5-1
gives the exception vector table format; the exception handler address should be written to the appropriate exception
number entry in the table.
c. Set up the exception priority, as explained in “Exception Priority” on page 35.
d. Enable the exception, as explained in “Enabling and Disabling Interrupts” on page 36.
5.12 Registers
5.13 Associated Documents
■ ARMv6-M Architecture Reference Manual – This document explains the ARM Cortex-M0 architecture, including the
instruction set, NVIC architecture, and CPU register descriptions.
Table 5-7. List of Registers
Register Name Description
CM0_ISER Interrupt Set-Enable Register
CM0_ICER Interrupt Clear Enable Register
CM0_ISPR Interrupt Set-Pending Register
CM0_ICPR Interrupt Clear-Pending Register
CM0_IPR Interrupt Priority Registers
CM0_ICSR Interrupt Control State Register
CM0_AIRCR Application Interrupt and Reset Control Register
CM0_SCR System Control Register
CM0_CCR Configuration and Control Register
CM0_SHPR2 System Handler Priority Register 2
CM0_SHPR3 System Handler Priority Register 3
CM0_SHCSR System Handler Control and State Register
CM0_SYST_CSR Systick Control and Status Register
CPUSS_CONFIG CPU Subsystem Configuration Register
CPUSS_SYSREQ System Request Register