PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 107
Timer, Counter, and PWM
16.3.1 Timer Mode
The timer mode is commonly used to measure the time of occurrence of an event or to measure the time difference between
two events.
16.3.1.1 Block Diagram
Figure 16-4. Timer Mode Block Diagram
16.3.1.2 How It Works
The timer can be configured to count in up, down, and up/down counting modes. It can also be configured to run in either con-
tinuous mode or one-shot mode. The following explains the working of the timer:
■ The timer is an up, down, and up/down counter.
❐ The current count value is stored in the count register (TCPWM_CNTx_COUNTER).
Note It is not recommended to write values to this register while the counter is running.
❐ The period value for the timer is stored in the period register.
■ The counter is re-initialized in different counting modes as follows:
❐ In the up counting mode, after the count reaches the period value, the count register is automatically reloaded with 0.
❐ In the down counting mode, after the count register reaches zero, the count register is reloaded with the value in the
period register.
❐ In the up/down counting modes, the count register value is not updated upon reaching the terminal values. Instead the
direction of counting changes when the count value reaches 0 or the period value.
■ The CC condition is generated when the count register value equals the compare register value. Upon this condition, the
compare register and buffer compare register switch their values if enabled by the AUTO_RELOAD_CC bit-field of the
counter control (TCPWM_CNT_CTRL) register. This condition can be used to generate an interrupt request.
Figure 16-5 shows the timer operational mode of the counter in four different counting modes. The period register contains
the maximum counter value.
■ In the up counting mode, a period value of A results in A+1 counter cycles (0 to A).
■ In the down counting mode, a period value of A results in A+1 counter cycles (A to 0).
■ In the two up/down counting modes (0 and 1), a period value of A results in 2*A counter cycles (0 to A and back to 0).
PERIOD
COUNTER
COMPARE
BUFFER
COMPARE
==
==
Reload
Start
Stop
Count
UN
OV
CC
TC
counter_clock
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