PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 55
8. Clocking System
The PSoC
®
4 clock system includes these clock resources:
■ Two internal clock sources:
❐ 24–48 MHz internal main oscillator (IMO) with ±2 percent accuracy across all frequencies with trim
❐ 40-kHz internal low-speed oscillator (ILO) (can be calibrated using the IMO)
■ External clock (EXTCLK) generated using a signal from an I/O pin
■ High-frequency clock (HFCLK) of up to 48 MHz, selected from IMO or external clock
❐ Dedicated prescaler for HFCLK
■ Low-frequency clock (LFCLK) sourced by ILO
■ Dedicated prescaler for system clock (SYSCLK) of up to 16 MHz sourced by HFCLK
■ Four peripheral clocks, each with a 16-bit divider
8.1 Block Diagram
Figure 8-1 gives a generic view of the clocking system in PSoC 4 devices.
Figure 8-1. Clocking System Block Diagram
IMO
ILO
EXTCLK
LFCLK
HFCLK
SYSCLK
Prescaler
SYSCLK
Peripheral
Divider 0
Peripheral
Divider 1
Peripheral
Divider 2
Peripheral
Divider 3
HFCLK
Predivider
SCBCLK
CSDCLK0
CSDCLK1
TCPWMCLK
WDT
Cortex-M0
CPU
SCB (I2C)
TCPWM
CSD
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