144 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Program and Debug Interface
18.6 PSoC 4 SWD Debug
Interface
Cortex-M0 DAP debugging features are classified into two
types: invasive debugging and noninvasive debugging. Inva-
sive debugging includes program halting and stepping,
breakpoints, and data watchpoints. Noninvasive debugging
includes instruction address profiling and device memory
access, which includes the flash memory, SRAM, and other
peripheral registers.
The DAP has three major debug subsystems:
■ Debug Control and Configuration registers
■ Breakpoint Unit (BPU) – provides breakpoint support
■ Debug Watchpoint (DWT) – provides watchpoint sup-
port. Trace is not supported in Cortex-M0 Debug.
See the
ARMv6-M Architecture Reference Manual for com-
plete details on the debug architecture.
18.6.1 Debug Control and Configuration
Registers
The debug control and configuration registers are used to
execute firmware debugging. The registers and their key
functions are as follows. See the
ARMv6-M Architecture
Reference Manual for complete bit level definitions of these
registers.
■ Debug Halting Control and Status Register
(CM0_DHCSR) – This register contains the control bits
to enable debug, halt the CPU, and perform a single-
step operation. It also includes status bits for the debug
state of the processor.
■ Debug Fault Status Register (CM0_DFSR) – This regis-
ter describes the reason a debug event has occurred
and includes debug events, which are caused by a CPU
halt, breakpoint event, or watchpoint event.
■ Debug Core Register Selector Register (CM0_DCRSR)
– This register is used to select the general-purpose reg-
ister in the Cortex-M0 CPU to which a read or write oper-
ation must be performed by the external debugger.
■ Debug Core Register Data Register (CM0_DCRDR) –
This register is used to store the data to write to or read
from the register selected in the CM0_DCRSR register.
■ Debug Exception and Monitor Control Register
(CM0_DEMCR) – This register contains the enable bits
for global debug watchpoint (DWT) block enable, reset
vector catch, and hard fault exception catch.
18.6.2 Breakpoint Unit (BPU)
The BPU provides breakpoint functionality on instruction
fetches. The Cortex-M0 DAP in PSoC 4 supports up to four
hardware breakpoints. Along with the hardware breakpoints,
any number of software breakpoints can be created by using
the BKPT instruction in the Cortex-M0. The BPU has two
types of registers.
■ The breakpoint control register (CM0_BP_CTRL) is used
to enable the BPU and store the number of hardware
breakpoints supported by the debug system (four for
CM0 DAP in the PSoC 4).
■ Each hardware breakpoint has a Breakpoint Compare
Register (CM0_BP_COMPx). It contains the enable bit
for the breakpoint, the compare address value, and the
match condition that will trigger a breakpoint debug
event. The typical use case is that when an instruction
fetch address matches the compare address of a break-
point, a breakpoint event is generated and the processor
is halted.
18.6.3 Data Watchpoint (DWT)
The DWT provides watchpoint support on a data address
access or a program counter (PC) instruction address.
Trace is not supported by the Cortex-M0 in PSoC 4. The
DWT supports two watchpoints. It also provides external
program counter sampling using a PC sample register,
which can be used for noninvasive coarse profiling of the
program counter. The most important registers in the DWT
are as follows.
■ The watchpoint compare (CM0_DWT_COMPx) registers
store the compare values that are used by the watch-
point comparator for the generation of watchpoint
events. Each watchpoint has an associated
DWT_COMPx register.
■ The watchpoint mask (CM0_DWT_MASKx) registers
store the ignore masks applied to the address range
matching in the associated watchpoints.
■ The watchpoint function (CM0_DWT_FUNCTIONx) reg-
isters store the conditions that trigger the watchpoint
events. They may be program counter watchpoint event
or data address read/write access watchpoint events. A
status bit is also set when the associated watchpoint
event has occurred.
■ The watchpoint comparator PC sample register
(CM0_DWT_PCSR) stores the current value of the pro-
gram counter. This register is used for coarse, non-inva-
sive profiling of the program counter register.
18.6.4 Debugging the PSoC 4 Device
The host debugs the target PSoC 4 by accessing the debug
control and configuration registers, registers in the BPU, and
registers in the DWT. All registers are accessed through the
SWD interface; the SWD debug port (SW-DP) in the Cortex-
M0 DAP converts the SWD packets to appropriate register
access through the DAP-AHB interface.
The first step in debugging the target PSoC 4 is to acquire
the SWD port. The acquire sequence consists of an SWD
line reset sequence and read of the DAP SWDID through
the SWD interface. The SWD port is acquired when the cor-
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