88 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Inter-Integrated Circuit (I2C)
15.2.5 I2C Interrupts
The fixed-function I
2
C block generates interrupts for the fol-
lowing conditions.
■ I2C Master
❐ I2C master lost arbitration
❐ I2C master received NACK
❐ I2C master received ACK
❐ I2C master sent STOP
❐ I2C bus error (unexpected stop/start condition
detected)
■ I2C Slave
❐ I2C slave lost arbitration
❐ I2C slave received NACK
❐ I2C slave received ACK
❐ I2C slave received STOP
❐ I2C slave received START
❐ I2C slave address matched
❐ I2C bus error (unexpected stop/start condition
detected)
■ TX
❐ TX FIFO has less entries than the value specified by
TRIGGER_LEVEL in SCB_TX_FIFO_CTRL
❐ TX FIFO is not full
❐ TX FIFO is empty
❐ TX FIFO overflow
❐ TX FIFO underflow
■ RX
❐ RX FIFO has less entries than the value specified by
TRIGGER_LEVEL in SCB_RX_FIFO_CTRL
❐ RX FIFO is full
❐ RX FIFO is not empty
❐ RX FIFO overflow
❐ RX FIFO underflow
■ I2C Externally Clocked
❐ Wake up request on address match
❐ I2C STOP detection at the end of each transfer
❐ I2C STOP detection at the end of a write transfer
❐ I2C STOP detection at the end of a read transfer
The I2C interrupt signal is hard-wired to the Cortex-M0 NVIC
and cannot be routed to external pins.
The interrupt output is the logical OR of the group of all pos-
sible interrupt sources. The interrupt is triggered when any
of the enabled interrupt conditions are met. Interrupt status
registers are used to determine the actual source of the
interrupt. For more information on interrupt registers, see the
PSoC 4000 Family: PSoC 4 Registers TRM.
15.2.6 Enabling and Initializing the I2C
The following section describes the method to configure the
I2C block for standard (non-EZ) mode and EZI2C mode.
15.2.6.1 Configuring for I2C Standard (Non-
EZ) Mode
The I2C interface must be programmed in the following
order.
1. Program protocol specific information using the
SCB_I2C_CTRL register according to Table 15-5. This
includes selecting master - slave functionality.
2. Program the generic transmitter and receiver information
using the SCB_TX_CTRL and SCB_RX_CTRL regis-
ters, as shown in Table 15-6.
a. Specify the data frame width.
b. Specify that MSB is the first bit to be transmitted/
received.
3. Program transmitter and receiver FIFO using the
SCB_TX_FIFO_CTRL and SCB_RX_FIFO_CTRL regis-
ters, respectively, as shown in Table 15-7.
a. Set the trigger level.
b. Clear the transmitter and receiver FIFO and Shift
registers.
4. Program the SCB_CTRL register to enable the I2C block
and select the I2C mode. These register bits are shown
in Table 15-8. For a complete description of the I2C reg-
isters, see the
PSoC 4000 Family: PSoC 4 Registers
TRM
.
Table 15-5. SCB_I2C_CTRL Register
Bits Name Value Description
30 SLAVE_MODE 1 Slave mode
31 MASTER_MODE 1 Master mode
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