Cypress PSoC 4000 Series - Non-Blocking Program Row

156 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Nonvolatile Memory Programming
Parameters
Return
19.5.10 Non-Blocking Program Row
This function is used when a flash row needs to be programmed by the CM0 CPU in a non-blocking manner, so that the CPU
can execute code from the SRAM when the program operation is being done. The explanation of non-blocking system calls is
explained in Blocking and Non-Blocking System Calls on page 148. While the program operation is being done, the CPU can
execute code from the SRAM. When the non-blocking program row system call is called, the user cannot call any other sys-
tem call function other than the Resume Non-Blocking function, which is required for the completion of the non-blocking write
operation.
Unlike the Non-Blocking Write Row system call, the Program system call only has a single phase. Therefore, the Resume
Non-Blocking function only needs to be called once from the SPC interrupt when using the Non-Blocking Program Row sys-
tem call.
Usage Requirements: Call the Configure Clock API before calling this function. The Configure Clock API ensures that the
charge pump clock (clk_pump) and the HF clock (clk_hf) are set to IMO at 48 MHz. Call the Load Flash Bytes function before
calling this function to load the data bytes that will be used for programming the row. In addition, the non-blocking program
row function can be called only from SRAM. This is because the CM0 CPU cannot execute code from flash while doing flash
program operations. If this function is called from flash memory, the result is undefined, and may return a bus error and trigger
a hard fault when the flash fetch operation is being done.
Parameters
Address Value to be Written Description
SRAM Address 32’hYY (32-bit wide, word-aligned SRAM address)
Bits [7:0] 0xB6 Key1
Bits [15:8] 0xDA Key2
Bits [31:16] Row ID
Row number to write
0x0000 – Row 0
CPUSS_SYSARG register
Bits [31:0] 32’hYY
32-bit word-aligned address of the SRAM that stores the first function
parameter (key1)
CPUSS_SYSREQ register
Bits [15:0] 0x0007 Non-Blocking Write Row opcode
Bits [31:16] 0x8000 Set SYSCALL_REQ bit
Address Return Value Description
CPUSS_SYSARG register
Bits [31:28] 0xA Success status code
Bits [27:0] 0xXXXXXXX Not used (don’t care)
Address Value to be Written Description
SRAM Address 32’hYY (32-bit wide, word-aligned SRAM address)
Bits [7:0] 0xB6 Key1
Bits [15:8] 0xDB Key2
Bits [31:16] Row ID
Row number to write
0x0000 – Row 0
CPUSS_SYSARG register