Cypress PSoC 4000 Series - Non-Blocking System Call Pseudo Code

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 159
Nonvolatile Memory Programming
19.7 Non-Blocking System Call Pseudo Code
This section contains pseudo code to demonstrate how to set up a non-blocking system call and execute code out of SRAM
during the flash programming operations.
#define REG(addr) (*((volatile uint32 *) (addr)))
#define CM0_ISER_REG REG( 0xE000E100 )
#define CPUSS_CONFIG_REG REG( 0x40100000 )
#define CPUSS_SYSREQ_REG REG( 0x40100004 )
#define CPUSS_SYSARG_REG REG( 0x40100008 )
#define ROW_SIZE_64 (64)
#define ROW_SIZE (ROW_SIZE_64)
/*Variable to keep track of how many times SPC ISR is triggered */
__ram int iStatusInt = 0x00;
__flash int main(void)
{
DoUserStuff();
/*CM0 interrupt enable bit for spc interrupt enable */
CM0_ISER_REG |= 0x00000040;
/*Set CPUSS_CONFIG.VECS_IN_RAM because SPC ISR should be in SRAM */
CPUSS_CONFIG_REG |= 0x00000001;
/*Call non-blocking write row API */
NonBlockingWriteRow();
/*End Program */
while(1);
}
__sram void SpcIntHandler(void)
{
/* Write key1, key2 parameters to SRAM */
REG( 0x20000000 ) = 0x0000DCB6;
/*Write the address of key1 to the CPUSS_SYSARG reg */
CPUSS_SYSARG_REG = 0x20000000;
/*Write the API opcode = 0x09 to the CPUSS_SYSREQ.COMMAND
* register and assert the sysreq bit
*/
CPUSS_SYSREQ_REG = 0x80000009;
/* Number of times the ISR has triggered */
iStatusInt ++;
}
__sram void NonBlockingWriteRow(void)
{
int iter;
/*Load the Flash page latch with data to write*/
* Write key1, key2, byte address, and macro sel parameters to SRAM
*/
REG( 0x20000000 ) = 0x0000D7B6;