28 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Cortex-M0 CPU
Use the MSR or CPS instruction to set or clear bit 0 of the PRIMASK register. If the bit is 0, exceptions are enabled. If the bit
is 1, all exceptions with configurable priority, that is, all exceptions except HardFault, NMI, and Reset, are disabled. See the
Interrupts chapter on page 31 for a list of exceptions.
4.6 Operating Modes
The Cortex-M0 processor supports two operating modes:
■ Thread Mode – used by all normal applications. In this mode, the MSP or PSP can be used. The CONTROL register bit 1
determines which stack pointer is used:
❐ 0 = MSP is the current stack pointer
❐ 1 = PSP is the current stack pointer
■ Handler Mode – used to execute exception handlers. The MSP is always used.
In thread mode, use the MSR instruction to set the stack pointer bit in the CONTROL register. When changing the stack
pointer, use an ISB instruction immediately after the MSR instruction. This ensures that instructions after the ISB execute
using the new stack pointer.
In handler mode, explicit writes to the CONTROL register are ignored, because the MSP is always used. The exception entry
and return mechanisms automatically update the CONTROL register.
4.7 Instruction Set
The Cortex-M0 implements a version of the Thumb instruction set, as Table 4-4 shows. For details, see the Cortex-M0
Generic User Guide.
An instruction operand can be an ARM register, a constant, or another instruction-specific parameter. Instructions act on the
operands and often store the result in a destination register. Many instructions are unable to use, or have restrictions on
using, the PC or SP for the operands or destination register.
27 – 25 – – Reserved
24 EPSR T
Thumb state bit. Must always be 1. Attempting to execute instructions when the T bit is 0
results in a HardFault exception.
23 – 6 – – Reserved
5 – 0 IPSR N/A
Exception number of current ISR:
0 = thread mode
1 = reserved
2 = NMI
3 = HardFault
4 – 10 = reserved
11 = SVCall
12, 13 = reserved
14 = PendSV
15 = SysTick
16 = IRQ0
…
24 = IRQ8
Table 4-3. Cortex-M0 PSR Bit Assignments
Bit PSR Register Name Usage
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