Cypress PSoC 4000 Series - Cortex-M0 Debug and Access Port (DAP); Debug Port (DP) Registers; Access Port (AP) Registers

142 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Program and Debug Interface
18.4 Cortex-M0 Debug and Access Port (DAP)
The Cortex-M0 program and debug interface includes a Debug Port (DP) and an Access Port (AP), which combine to form the
DAP. The debug port implements the state machine for the SWD interface protocol that enables communication with the host
device. It also includes registers for the configuration of access port, DAP identification code, and so on. The access port con-
tains registers that enable the external device to access the Cortex-M0 DAP-AHB interface. Typically, the DP registers are
used for a one time configuration or for error detection purposes, and the AP registers are used to perform the programming
and debugging operations. Complete architecture details of the DAP is available in the
ARM® Debug Interface v5 Architec-
ture Specification
.
18.4.1 Debug Port (DP) Registers
Table 18-3 shows the Cortex-M0 DP registers used for programming and debugging, along with the corresponding SWD
address bit selections. The APnDP bit is always zero for DP register accesses. Two address bits (A[3:2]) are used for select-
ing among the different DP registers. Note that for the same address bits, different DP registers can be accessed depending
on whether it is a read or a write operation. See the
ARM® Debug Interface v5 Architecture Specification for details on all of
the DP registers.
18.4.2 Access Port (AP) Registers
Table 18-4 lists the main Cortex-M0 AP registers that are used for programming and debugging, along with the corresponding
SWD address bit selections. The APnDP bit is always one for AP register accesses. Two address bits (A[3:2]) are used for
selecting the different AP registers.
Table 18-3. Main Debug Port (DP) Registers
Register APnDP
Address
A[3:2]
RnW Full Name Register Functionality
ABORT 0 (DP) 2b00 0 (W) AP Abort Register
This register is used to force a DAP abort and to clear the
error and sticky flag conditions.
IDCODE 0 (DP) 2b00 1 (R)
Identification Code
Register
This register holds the SWD ID of the Cortex-M0 CPU, which
is 0x0BB11477.
CTRL/STAT 0 (DP) 2b01 X (R/W)
Control and Status
Register
This register allows control of the DP and contains status
information about the DP.
SELECT 0 (DP) 2b10 0 (W) AP Select Register
This register is used to select the current AP. In PSoC 4, there
is only one AP, which interfaces with the DAP AHB.
RDBUFF 0 (DP) 2b11 1 (R) Read Buffer Register This register holds the result of the last AP read operation.
Table 18-4. Main Access Port (AP) Registers
Register APnDP
Address
A[3:2]
RnW Full Name Register Functionality
CSW 1 (AP) 2b00 X (R/W)
Control and Status
Word Register
(CSW)
This register configures and controls accesses through the
memory access port to a connected memory system (which is
the PSoC 4 Memory map)
TAR 1 (AP) 2b01 X (R/W)
Transfer Address
Register
This register is used to specify the 32-bit memory address to
be read from or written to
DRW 1 (AP) 2b11 X (R/W)
Data Read and Write
Register
This register holds the 32-bit data read from or to be written to
the address specified in the TAR register