PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 155
Nonvolatile Memory Programming
Parameters
Return
19.5.9 Non-Blocking Write Row
This function is used when a flash row needs to be written by the CM0 CPU in a non-blocking manner, so that the CPU can
execute code from SRAM while the write operation is being done. The explanation of non-blocking system calls is explained
in Blocking and Non-Blocking System Calls on page 148.
The non-blocking write row system call has three phases: Pre-program, Erase, Program. Pre-program is the step in which all
of the bits in the flash row are written a ‘1’ in preparation for an erase operation. The erase operation clears all of the bits in
the row, and the program operation writes the new data to the row.
While each phase is being executed, the CPU can execute code from SRAM. When the non-blocking write row system call is
initiated, the user cannot call any system call function other than the Resume Non-Blocking function, which is required for
completion of the non-blocking write operation. After the completion of each phase, the SPC triggers its interrupt. In this inter-
rupt, call the Resume Non-Blocking system call.
Note The device firmware must not attempt to put the device to sleep during a non-blocking write row. This action will reset
the page latch buffer and the flash will be written with all zeroes.
Usage Requirements: Call the Configure Clock API before calling this function. The Configure Clock API ensures that the
charge pump clock (clk_pump) and the HF clock (clk_hf) are set to IMO at 48 MHz. Call the Load Flash Bytes function before
calling this function to load the data bytes that will be used for programming the row. In addition, the non-blocking write row
function can be called only from the SRAM. This is because the CM0 CPU cannot execute code from flash while doing the
flash erase program operations. If this function is called from the flash memory, the result is undefined, and may return a bus
error and trigger a hard fault when the flash fetch operation is being done.
Address Value to be Written Description
CPUSS_SYSARG register
Bits [7:0] 0xB6 Key1
Bits [15:8] 0xE0 Key2
Bits [23:16] Device Protection Byte
Parameter applicable only for Flash Macro 0
0x01 – OPEN mode
0x02 – PROTECTED mode
0x04 – KILL mode
Bits [31:24] Flash Macro Select
0x00 – Flash Macro 0
0x01 – Flash Macro 1
CPUSS_SYSREQ register
Bits [15:0] 0x000D Write Protection opcode
Bits [31:16] 0x8000 Set SYSCALL_REQ bit
Address Return Value Description
CPUSS_SYSARG register
Bits [31:28] 0xA Success status code
Bits [27:24] 0xX Not used (don’t care)
Bits [23:0] 0x000000
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