PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 57
Clocking System
8.2.1.1 Startup Behavior
After reset, the IMO is configured for 24-MHz operation.
During the “boot” portion of startup, trim values are read
from flash and the IMO is configured to achieve datasheet
specified accuracy. The HFCLK predivider is initially set to a
divide value of 4 to reduce current consumption at startup.
8.2.2 Internal Low-speed Oscillator
The internal low-speed oscillator operates with no external components and outputs a stable clock at 40-kHz nominal. The
ILO is relatively low power and low accuracy. It can be calibrated using a higher accuracy, high-frequency clock to improve
accuracy. The ILO is available in all power modes. The ILO is always used as the system low-frequency clock LFCLK in the
device. The ILO is a relatively inaccurate (±60 percent overvoltage and temperature) oscillator, which is used to generate low-
frequency clocks. If calibrated against the IMO when in operation, the ILO is accurate to ±10 percent for stable temperature
and voltage. The ILO is recommended to be always on, because it is the source of the WDT, which is required for reliable sys-
tem operation. The ILO can be disabled by clearing the ENABLE bit in the CLK_ILO_CONFIG register. The WDT reset must
be disabled before disabling the ILO. Otherwise, any register write to disable the ILO will be ignored. Enabling the WDT reset
will automatically enable the ILO.
Note Disabling the ILO reset is not recommended if:
■ WDT protection is required against firmware crashes
■ WDT protection is required against the power supply events that produce sudden brownout events that may in turn com-
promise the CPU functionality.
See the Watchdog Timer chapter on page 73 for details.
8.2.3 External Clock (EXTCLK)
The external clock (EXTCLK) is a MHz range clock that can be generated from a signal on a designated PSoC 4 pin. This
clock may be used instead of the IMO as the source of the system high-frequency clock, HFCLK. The allowable range of
external clock frequencies is0–16 MHz. The device always starts up using the IMO and the external clock must be enabled in
user mode; so the device cannot be started from a reset, which is clocked by the external clock.
When manually configuring a pin as the input to the EXTCLK, the drive mode of the pin must be set to high-impedance digital
to enable the digital input buffer. See the I/O System chapter on page 45 for more details.
8.3 Clock Distribution
PSoC 4 clocks are developed and distributed throughout the device, as shown in Figure 8-1. The distribution configuration
options are as follows:
■ HFCLK input selection
■ HFCLK predivider configuration
■ SYSCLK prescaler configuration
■ Peripheral divider configuration
8.3.1 HFCLK Input Selection
HFCLK in PSoC 4 has two input options: IMO and EXTCLK. The HFCLK input is selected using the CLK_SELECT register’s
DIRECT_SEL bits, as described in Table 8-2.
Table 8-2. HFCLK Input Selection Bits DIRECT_SEL
Name Description
DIRECT_SEL[2:0]
HFCLK input clock selection
0: IMO. Uses the IMO as the source of the HFCLK
1: EXTCLK. Uses the EXTCLK as the source of the HFCLK
2–7: Reserved. Do not use
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