Cypress PSoC 4000 Series - 19.5.4 Write Row

152 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Nonvolatile Memory Programming
19.5.4 Write Row
This function erases and then programs the addressed row of flash with the data in the page latch buffer. If all data in the page
latch buffer is 0, then the program is skipped. The parameters for this function are stored in SRAM. The start address of the
stored parameters is written to the CPUSS_SYSARG register. This function clears the page latch buffer contents after the row
is programmed.
Usage Requirements: Call the Configure Clock API before calling this function. The Configure Clock API ensures that the
charge pump clock (clk_pump) and the HF clock (clk_hf) are set to IMO at 48 MHz. Call the Load Flash Bytes function before
calling this function. This function can do a write operation only if the corresponding flash row is not write protected.
Note that the SROM does not modify, enable, or disable any clock during any flash operation. Refer to the
CLK_IMO_CONFIG register in the
PSoC 4000 Family: PSoC 4 Registers TRM for more information.
Parameters
Return
19.5.5 Program Row
This function programs the addressed row of the flash with data in the page latch buffer. If all data in the page latch buffer is 0,
then the program is skipped. The row must be in an erased state before calling this function. It clears the page latch buffer
contents after the row is programmed.
Usage Requirements: Call the Configure Clock API before calling this function. The Configure Clock API ensures that the
charge pump clock (clk_pump) and the HF clock (clk_hf) are set to IMO at 48 MHz. Call the Load Flash Bytes function before
calling this function. The row must be in an erased state before calling this function. This function can do a program operation
only if the corresponding flash row is not write-protected.
Parameters
Address Value to be Written Description
SRAM Address: 32’hYY (32-bit wide, word-aligned SRAM address)
Bits [7:0] 0xB6 Key1
Bits [15:8] 0xD8 Key2
Bits [31:16] Row ID
Row number to write
0x0000 – Row 0
CPUSS_SYSARG register
Bits [31:0] 32’hYY
32-bit word-aligned address of the SRAM that
stores the first function parameter (key1)
CPUSS_SYSREQ register
Bits [15:0] 0x0005 Write Row opcode
Bits [31:16] 0x8000 Set SYSCALL_REQ bit
Address Return Value Description
CPUSS_SYSARG register
Bits [31:28] 0xA Success status code
Bits [27:0] 0xXXXXXXX Not used (don’t care)
Address Value to be Written Description
SRAM Address: 32’hYY (32-bit wide, word-aligned SRAM address)
Bits [7:0] 0xB6 Key1
Bits [15:8] 0xD9 Key2
Bits [31:16] Row ID
Row number to program
0x0000 – Row 0