Cypress PSoC 4000 Series - 7.3 I;O Cell Architecture

46 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
I/O System
Figure 7-1. GPIO Interface Overview
GPIO pins are connected to I/O cells. These cells are equipped with an input buffer for the digital input, providing high input
impedance and a driver for the digital output signals. The digital peripherals connect to the I/O cells via the high-speed I/O
matrix (HSIOM). HSIOM contains multiplexers to connect between a peripheral selected by the user and the pin. The
CapSense block is connected to the GPIO pins through the AMUX buses.
7.3 I/O Cell Architecture
Figure 7-2 shows the I/O cell architecture. It comprises of an input buffer and an output driver. This architecture is present in
every GPIO cell. It connects to the HSIOM multiplexers for the digital input and the output signal. Analog peripherals connect
directly to the pin.
High Speed IO Matrix
(HSIOM)
GPIO
Configuration
GPIO Interrupt
GPIO Pin
Interface
GPIO Port Control
CSD
Controller
Fixed
Function
Digital
Peripherals
(TCPWM,
I2C)
CapSense
Pin
AMUXBUS-A
AMUXBUS-B
IO Cell