PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 119
Timer, Counter, and PWM
16.3.5 Pulse Width Modulation with Dead Time Mode
Dead time is used to delay the transitions of both ‘line_out’ and ‘line_out_compl’ signals. It separates the transition edges of
these two signals by a specified time interval. Two complementary output lines 'dt_line' and 'dt_line_compl' are derived from
these two lines. During the dead band period, both compare output and complement compare output are at logic ‘0’ for a fixed
period. The dead band feature allows the generation of two non-overlapping PWM pulses. A maximum dead time of 255
clocks can be generated using this feature.
16.3.5.1 Block Diagram
Figure 16-14. PWM-DT Mode Block Diagram
16.3.5.2 How It Works
The PWM operation with Dead Time mode occurs as fol-
lows:
■ On the rising edge of the PWM line_out, depending upon
UN, OV, and CC conditions, the dead time block sets the
dt_line and dt_line_compl to '0'.
■ The dead band period is loaded and counted for the
period configured in the register.
■ When the dead band period is complete, dt_line is set to
'1'.
■ On the falling edge of the PWM line_out depending upon
UN, OV, and CC conditions, the dead time block sets the
dt_line and dt_line_compl to '0'.
■ The dead band period is loaded and counted for the
period configured in the register.
■ When the dead band period has completed,
dt_line_compl is set to '1'.
■ A dead band period of zero has no effect on the dt_line
and is the same as line_out.
■ When the duration of the dead time equals or exceeds
the width of a pulse, the pulse is removed.
This mode follows PWM mode and supports the following
features available with that mode:
■ Various output alignment modes
■ Two complementary output lines, dt_line and
dt_line_compl, derived from PWM "line_out" and "line
_out_compl", respectively
❐ Stop/kill event with synchronous and asynchronous
modes
❐ Conditional switch event for compare and buffer
compare registers and period and buffer period reg-
isters
This mode does not support clock prescaling.
Figure 16-15 illustrates how the complementary output lines
"dt_line" and "dt_line_compl" are generated from the PWM
output line, "line_out".
PERIOD
COUNTER
COMPARE
BUFFER COMPARE
==
Reload
Start
Stop
Switch
CC
TC
counter_clock
BUFFER PERIOD
PWM
dt_line
Count
Dead Time
dt_line_compl
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