118 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Timer, Counter, and PWM
A kill event can be programmed to be asynchronous or synchronous, as shown in Table 16-8.
In the synchronous kill, PWM cannot be started before the next TC. To restart the PWM immediately after kill input is
removed, kill event should be asynchronous (see Table 16-8). The generated stop event disables both output lines. In this
case, the reload event can use the same trigger input signal but should be used in falling edge detection mode.
16.3.4.5 Configuring Counter for PWM Mode
The steps to configure the counter for the PWM mode of operation and the affected register bits are as follows.
1. Disable the counter by writing '0' to the COUNTER_ENABLED field of the TCPWM_CTRL register.
2. Select PWM mode by writing '100' to the MODE[26:24] field of the TCPWM_CNT_CTRL register.
3. Set clock prescaling by writing to the GENERIC[15:8] field of the TCPWM_CNT_CTRL register, as shown in Table 16-1.
4. Set the required 16-bit period in the TCPWM_CNT_PERIOD register and the buffer period value in the
TCPWM_CNT_PERIOD_BUFF register to switch values, if required.
5. Set the 16-bit compare value in the TCPWM_CNT_CC register and buffer compare value in the TCPWM_CNT_CC_BUFF
register to switch values, if required.
6. Set the direction of counting by writing to the UP_DOWN_MODE[17:16] field of the TCPWM_CNT_CTRL register to con-
figure left-aligned, right-aligned, or center-aligned PWM, as shown in Table 16-6.
7. Set the PWM_STOP_ON_KILL and PWM_SYNC_KILL fields of the TCPWM_CNT_CTRL register as required.
8. Set the TCPWM_CNT_TR_CTRL0 register to select the trigger that causes the event (Reload, Start, Kill, Switch, and
Count).
9. Set the TCPWM_CNT_TR_CTRL1 register to select the edge that causes the event (Reload, Start, Kill, Switch, and
Count).
10. line_out and line_out_compl can be controlled by the TCPWM_CNT_TR_CTRL2 register to set, reset, or invert upon CC,
OV, and UN conditions.
11. If required, set the interrupt upon TC or CC condition, as shown in “Interrupts” on page 104.
12. Enable the counter by writing '1' to the COUNTER_ENABLED field of the TCPWM_CTRL register. A start trigger must be
provided through firmware (TCPWM_CMD register) to start the counter if the hardware start signal is not enabled.
Table 16-8. Field Setting for Synchronous/Asynchronous Kill
PWM_SYNC_KILL Field Comments
0 An asynchronous kill event lasts as long as it is present. This event requires pass through mode.
1
A synchronous kill event disables the output lines until the next TC event. This event requires rising
edge mode.
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