34 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Interrupts
of the startup code in flash memory. The CPU starts execut-
ing code out of this address. Note that the reset exception
address in the SRAM vector table will never be used
because the device comes out of reset with the flash vector
table selected. The register configuration to select the
SRAM vector table can be done only as part of the startup
code in flash after the reset is de-asserted.
5.4.2 Non-Maskable Interrupt (NMI)
Exception
Non-maskable interrupt (NMI) is the highest priority excep-
tion other than reset. It is always enabled with a fixed priority
of –2. There are two ways to trigger an NMI exception in the
device:
■ NMI exception by setting NMIPENDSET bit (user NMI
exception):
An NMI exception can be triggered in soft-
ware by setting the NMIPENDSET bit in the interrupt
control state register (CM0_ICSR register). Setting this
bit will execute the NMI handler pointed to by the active
vector table (flash or SRAM vector table).
■ System Call NMI exception: This exception is used for
nonvolatile programming operations such as flash write
operation and flash checksum operation. It is triggered
by setting the SYSCALL_REQ bit in the
CPUSS_SYSREQ register. An NMI exception triggered
by SYSCALL_REQ bit always executes the NMI excep-
tion handler code that resides in SROM. Flash or SRAM
exception vector table is not used for system call NMI
exception. The NMI handler code in SROM is not read/
write accessible because it contains nonvolatile pro-
gramming routines that should not be modified by the
user.
5.4.3 HardFault Exception
HardFault is an always-enabled exception that occurs
because of an error during normal or exception processing.
HardFault has a fixed priority of –1, meaning it has higher
priority than any exception with configurable priority. Hard-
Fault exception is a catch-all exception for different types of
fault conditions, which include executing an undefined
instruction and accessing an invalid memory addresses.
The CM0 CPU does not provide fault status information to
the HardFault exception handler, but it does permit the han-
dler to perform an exception return and continue execution
in cases where software has the ability to recover from the
fault situation.
5.4.4 Supervisor Call (SVCall) Exception
Supervisor Call (SVCall) is an always-enabled exception
caused when the CPU executes the SVC instruction as part
of the application code. Application software uses the SVC
instruction to make a call to an underlying operating system
and provide a service. This is known as a supervisor call.
The SVC instruction enables the application to issue a
supervisor call that requires privileged access to the system.
Note that the CM0 in PSoC 4 uses a privileged mode for the
system call NMI exception, which is not related to the SVCall
exception. (See the Chip Operational Modes chapter on
page 73 for details on privileged mode.) There is no other
privileged mode support for SVCall at the architecture level
in the device. The application developer must define the
SVCall exception handler according to the end application
requirements.
The priority of a SVCall exception can be configured to a
value between 0 and 3 by writing to the two bit fields
PRI_11[31:30] of the System Handler Priority Register 2
(SHPR2). When the SVC instruction is executed, the SVCall
exception enters the pending state and waits to be serviced
by the CPU. The SVCALLPENDED bit in the System Han-
dler Control and State Register (SHCSR) can be used to
check or modify the pending status of the SVCall exception.
5.4.5 PendSV Exception
PendSV is another supervisor call related exception similar
to SVCall, normally being software-generated. PendSV is
always enabled and its priority is configurable. The PendSV
exception is triggered by setting the PENDSVSET bit in the
Interrupt Control State Register, CM0_ICSR. On setting this
bit, the PendSV exception enters the pending state, and
waits to be serviced by the CPU. The pending state of a
PendSV exception can be cleared by setting the PENDSV-
CLR bit in the Interrupt Control State Register, CM0_ICSR.
The priority of a PendSV exception can be configured to a
value between 0 and 3 by writing to the two bit fields
PRI_14[23:22] of the System Handler Priority Register 3
(CM0_SHPR3). See the ARMv6-M Architecture Reference
Manual for more details.
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