86 PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D
Inter-Integrated Circuit (I2C)
15.2.3 Easy I2C (EZI2C) Protocol
The Easy I2C (EZI2C) protocol is a unique communication
scheme built on top of the I
2
C protocol by Cypress. It uses a
software wrapper around the standard I
2
C protocol to com-
municate to an I
2
C slave using indexed memory transfers.
This removes the need for CPU intervention at the level of
individual frames.
The EZI2C protocol defines an 8-bit address that indexes a
memory array (8-bit wide 32 locations) located on the slave
device. Five lower bits of the EZ address are used to
address these 32 locations. The number of bytes transferred
to or from the EZI2C memory array can be found by compar-
ing the EZ address at the START event and the EZ address
at the STOP event.
Note The I
2
C block has a hardware FIFO memory, which is
16 bits wide and 16 locations deep with byte write enable.
The access methods for EZ and non-EZ functions are differ-
ent. In non-EZ mode, the FIFO is split into TXFIFO and
RXFIFO. Each has 16-bit wide eight locations. In EZ mode,
the FIFO is used as a single memory unit with 8-bit wide 32
locations.
EZI2C has two types of transfers: a data write from the mas-
ter to an addressed slave memory location, and a read by
the master from an addressed slave memory location.
15.2.3.1 Memory Array Write
An EZ write to a memory array index is by means of an I
2
C
write transfer. The first transmitted write data is used to send
an EZ address from the master to the slave. The five lowest
significant bits of the write data are used as the "new" EZ
address at the slave. Any additional write data elements in
the write transfer are bytes that are written to the memory
array. The EZ address is automatically incremented by the
slave as bytes are written into the memory array. If the num-
ber of continuous data bytes written to the EZI2C buffer
exceeds EZI2C buffer boundary, it overwrites the last loca-
tion for every subsequent byte.
15.2.3.2 Memory Array Read
An EZ read from a memory array index is by means of an
I
2
C read transfer. The EZ read relies on an earlier EZ write
to have set the EZ address at the slave. The first received
read data is the byte from the memory array at the EZ
address memory location. The EZ address is automatically
incremented as bytes are read from the memory array. The
address wraps around to zero when the final memory loca-
tion is reached.
Figure 15-4. EZI2C Write and Read Data Transfer
LEGEND :
MS
B
LS
B
SDA
SCL
START Slave address (7 bits) Write ACK ACKEZ address(8 bits) STOP
Write data transfer(single write data)
MSB
LSB
START Slave address (7 bits) Read ACK ACKRead Data(8 bits) STOP
Read data transfer(single read data)
SDA
SCL
SDA: Serial Data Line
SCL: Serial Clock Line(always driven by the master)
Slave Transmit / Master Receive
Write Data(8 bits) ACK
EZ address
Address
Data
EZ Buffer
(32 bytes SRAM)
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