Cypress PSoC 4000 Series - Page 85

PSoC 4000 Family: PSoC 4 Architecture TRM, Document No. 001-89309 Rev. *D 85
Inter-Integrated Circuit (I2C)
15.2.2.1 Write Transfer
Figure 15-2. Master Write Data Transfer
■ A typical write transfer begins with the master generating a START condition on the I
2
C bus. The master then writes a 7-
bit I
2
C slave address and a write indicator ('0') after the START condition. The addressed slave transmits an acknowl-
edgement byte by pulling the data line low during the ninth bit time.
■ If the slave address does not match any of the slave devices or if the addressed device does not want to acknowledge the
request, it transmits a no acknowledgement (NACK) by not pulling the SDA line low. The absence of an acknowledge-
ment, results in an SDA line value of '1' due to the pull-up resistor implementation.
■ If no acknowledgement is transmitted by the slave, the master may end the write transfer with a STOP event. The master
can also generate a repeated START condition for a retry attempt.
■ The master may transmit data to the bus if it receives an acknowledgement. The addressed slave transmits an acknowl-
edgement to confirm the receipt of every byte of data written. Upon receipt of this acknowledgement, the master may
transmit another data byte.
■ When the transfer is complete, the master generates a STOP condition.
15.2.2.2 Read Transfer
Figure 15-3. Master Read Data Transfer
■ A typical read transfer begins with the master generating a START condition on the I
2
C bus. The master then writes a 7-
bit I
2
C slave address and a read indicator ('1') after the START condition. The addressed slave transmits an acknowledge-
ment by pulling the data line low during the ninth bit time.
■ If the slave address does not match with that of the connected slave device or if the addressed device does not want to
acknowledge the request, a no acknowledgement (NACK) is transmitted by not pulling the SDA line low. The absence of
an acknowledgement, results in an SDA line value of '1' due to the pull-up resistor implementation.
■ If no acknowledgement is transmitted by the slave, the master may end the read transfer with a STOP event. The master
can also generate a repeated START condition for a retry attempt.
■ If the slave acknowledges the address, it starts transmitting data after the acknowledgement signal. The master transmits
an acknowledgement to confirm the receipt of each data byte sent by the slave. Upon receipt of this acknowledgement,
the addressed slave may transmit another data byte.
■ The master can send a NACK signal to the slave to stop the slave from sending data bytes. This completes the read
transfer.
■ When the transfer is complete, the master generates a STOP condition.
MSB
LSB
SDA
SCL
START Slave address (7 bits)
Write
ACK
ACKData(8 bits)
STOP
Write data transfer(Master writes the data)
LEGEND :
SDA: Serial Data Line
SCL: Serial Clock Line(always driven by the master)
Slave Transmit / Master Receive
MSB
LSB
START Slave address (7 bits)
Read
ACK
ACKData(8 bits)
STOP
Read data transfer(Master reads the data)
SDA
SCL
LEGEND :
SDA: Serial Data Line
SCL: Serial Clock Line(always driven by the master)
Slave Transmit / Master Receive